AT90PWM1-16MU Atmel, AT90PWM1-16MU Datasheet - Page 77
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AT90PWM1-16MU
Manufacturer Part Number
AT90PWM1-16MU
Description
IC AVR PWM 8KB FLASH 16MHZ 32QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM1-16SU.pdf
(297 pages)
Specifications of AT90PWM1-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.0.4
4378C–AVR–09/08
General Timer/Counter Control Register – GTCCR
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can
be configured to the same value without the risk of one of them advancing during configuration.
When the TSM bit is written to zero, the PSRSYNC bit is cleared by hardware, and the
Timer/Counters start counting simultaneously.
• Bit6 – ICPSEL1: Timer 1 Input Capture selection
Bit
Read/Write
Initial Value
PSRSYNC
1. The synchronization logic on the input pins (
clk
T0
T1
I/O
Synchronization
Synchronization
TSM
R/W
7
0
ExtClk
ICPSEL1
R/W
6
0
< f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
clk
Clear
T1
R
4
–
0
Tn/T0)
R
3
–
0
is shown in
R
2
–
0
(1)
Figure
R
1
–
0
AT90PWM1
13-1.
clk
PSRSYNC
T0
R/W
clk_I/O
0
0
/2.5.
GTCCR
77
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