ATTINY2313A-MUR Atmel, ATTINY2313A-MUR Datasheet - Page 50

• Manufacturer Part Number: ATTINY2313A-MUR
• Description: MCU AVR 2K FLASH 20MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

9.3
9.3.1
9.3.2
50
Register Description
ATtiny2313A/4313
MCUCR – MCU Control Register
GIMSK – General Interrupt Mask Register
The External Interrupt Control Register contains control bits for interrupt sense control.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt
Table 9-2.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-3.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x3B (0x5B)
Read/Write
Initial Value
ISC11
ISC01
0
0
1
1
0
0
1
1
ISC10
Interrupt 1 Sense Control
Interrupt 0 Sense Control
PUD
R/W
ISC00
7
0
0
1
0
1
INT1
R/W
7
0
0
1
0
1
SM1
R/W
Table
Table
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
6
0
INT0
R/W
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
6
0
9-2. The value on the INT1 pin is sampled before detecting edges.
9-3. The value on the INT0 pin is sampled before detecting edges.
R/W
SE
5
0
PCIE0
R/W
5
0
SM0
R/W
0
4
PCIE2
R/W
4
0
ISC11
R/W
3
0
PCIE1
R/W
3
0
ISC10
R/W
2
0
R
2
–
0
ISC01
R/W
1
0
ISC00
R
1
–
0
R/W
0
0
MCUCR
R
0
–
0
8246A–AVR–11/09
GIMSK