ATTINY2313A-MUR Atmel, ATTINY2313A-MUR Datasheet - Page 152

• Manufacturer Part Number: ATTINY2313A-MUR
• Description: MCU AVR 2K FLASH 20MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

15.8
15.8.1
15.8.2
15.8.3
152
Register Description
ATtiny2313A/4313
UDR – USART MSPIM I/O Data Register
UCSRA – USART MSPIM Control and Status Register A
UCSRB – USART MSPIM Control and Status Register B
The following section describes the registers used for SPI operation using the USART.
The function and bit description of the USART data register (UDR) in MSPI mode is identical to
normal USART operation. See “UDR – USART I/O Data Register” on page 136.
• Bit 7 – RXC: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXC bit will become zero. The RXC Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIE bit).
• Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDR). The TXC Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXC Flag can generate a Transmit Complete interrupt (see descrip-
tion of the TXCIE bit).
• Bit 5 – UDRE: USART Data Register Empty
The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is
one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data
Register Empty interrupt (see description of the UDRIE bit). UDRE is set after a reset to indicate
that the Transmitter is ready.
• Bit 4:0 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRA is written.
• Bit 7 – RXCIE: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the RXC bit in UCSRA is set.
Bit
0x0B (0x2B)
Read/Write
Initial Value
Bit
0x0A (0x2A)
Read/Write
Initial Value
RXC
R
7
0
RXCIE
R/W
7
0
TXC
R/W
6
0
TXCIE
R/W
6
0
UDRE
R
5
0
UDRIE
R/W
5
0
R
4
0
-
RXEN
R/W
4
0
R
3
0
-
TXEN
R/W
3
0
R
2
1
-
R
2
1
-
R
1
1
-
R
1
1
-
R
0
0
-
R
0
0
-
8246A–AVR–11/09
UCSRB
UCSRA