M30625FGPGP#U9C Renesas Electronics America, M30625FGPGP#U9C Datasheet - Page 214
![IC M16C MCU FLASH 128LQFP](/photos/12/29/122943/m30625fgpgp_u9c_sml.jpg)
M30625FGPGP#U9C
Manufacturer Part Number
M30625FGPGP#U9C
Description
IC M16C MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.2
Table 17.5
NOTES:
Transfer Data Format
Transfer Clock
Transmission, Reception
Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
1. If an overrun error occurs, the receive data of UiRB register will be indeterminate. The IR bit in the SiRIC
2. The U0IRS and U1IRS bits are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data
format. Table 17.5 lists the UART Mode Specifications.
register does not change.
from the UARTi receive register to the UiRB register.
Jan 10, 2006
Clock Asynchronous Serial I/O (UART) Mode
Item
UART Mode Specifications
Page 197 of 390
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (16(n+1))
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
• fEXT: Input from CLKi pin n :Setting value of UiBRG register 00h to FFh
Selectable from CTS function, RTS function or CTS/RTS function disable
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = L
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
For transmission, one of the following conditions can be selected
• The UiIRS bit
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first, MSB first selection
• Serial data logic switch
• TXD, RXD I/O polarity switch
• Separate CTS/RTS pins (UART0)
register to the UARTi transmit register (at start of transmission)
from the UARTi transmit register
completion of reception)
fj = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of UiBRG register 00h to FFh
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the bit one before the last stop bit of the next data
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of “1” in parity and character
bits does not match the number of “1” set
This flag is set to “1” when any of the overrun, framing or parity errors occur
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
This function reverses the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
CTS0 and RTS0 are input/output from separate pins
(3)
(2)
(1)
(3)
= 0 (transmit buffer empty): when transferring data from the UiTB
Specification
17. Serial Interface
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