M30625FGPGP#U9C Renesas Electronics America, M30625FGPGP#U9C Datasheet - Page 186
![IC M16C MCU FLASH 128LQFP](/photos/12/29/122943/m30625fgpgp_u9c_sml.jpg)
M30625FGPGP#U9C
Manufacturer Part Number
M30625FGPGP#U9C
Description
IC M16C MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 16.4
Timer B2 Interrupt Generation Frequency Set Counter
b7
NOTES :
Timer Ai, Ai-1 Register (i = 1, 2, 4)
(b15)
b7
NOTES :
1.
2.
3. If the INV00 bit is set to “1”, the first interrupt is generated w hen Timer B2 underflow s n-1 times, n being the value set
1.
2
3
4
5
6
7
Use the MOV instruction to set the ICTB2 register.
If the INV01 bit is set to “1”, set the ICTB2 register w hen the TB2S bit is set to “0” (Timer B2 counter stopped).
If the INV01 bit is set to “0” and the TB2S bit to “1” (Timer B2 counter start), do not set the ICTB2 register w hen Timer
B2 underflow s.
in the ICTB2 counter. Subsequent interrupts are generated every n times Timer B2 underflow s.
Jan 10, 2006
Use a 16-bit data for read and w rite.
If the TAi or TAi1 register is set to “0000h”, no counters start and no Timer Ai interrupt is generated.
Use the MOV instruction to set the TAi and TAi1 registers.
When the INV15 bit in the INVC1 register is set to “0” (dead timer enabled), phase sw itches from an inactive level to
an active level w hen the dead time timer stops.
When the INV11 bit is set to “0” (three-phase mode 0), the value of the TAi register is transferred to the reload
register by a Timer Ai start trigger.
When the INV11 bit is set to “1” (three-phase mode 1), the value of the TAi1 register is first transferred to the
reload register by a Timer Ai start trigger. Then, the value of the TAi register is transferred by the next trigger. The
values of the TAi1 and TAi registers are transferred alternately to the reload register w ith every Timer Ai start
trigger.
Do not w rite to these registers w hen the Timer B2 underflow s.
Follow the procedure below to set the TAi1 register.
(a) Write value to the TAi1 register,
(b) Wait one Timer Ai count source cycle, and
(c) Write the same value as (a) to the TAi1 register.
ICTB2, TA1, TA2, TA4, TA11, TA21 and TA41 Registers
b0
(b8)
b0
When the INV01 bit is set to “0” (the ICTB2 counter increments w henever
Timer B2 underflow s) and the setting value is n , Timer B2 interrupt is
generated every n th time Timer B2 underflow occurs.
When the INV01 bit is set to “1” (the INV00 bit selects count timing of the
ICTB2 counter) and setting value is n , Timer B2 interrupt is generated
every n th time Timer B2 underflow meeting the condition selected in the
INV00 bit occurs.
Nothing is assigned. When w rite, set to “0”.
b7
Symbol
If setting value is n , the timer stops w hen the n th count source is
counted after a start trigger is generated.
Positive phase changes to negative phase, and vice versa, w hen
Timers A1, A2 and A4 stop.
ICTB2
Page 169 of 390
b0
(1, 2, 3, 4, 5, 6, 7)
TA1, TA2
TA4
TA11, TA21 0343h to 0342h, 0345h to 0344h
TA41
Symbol
Function
Function
0389h to 0388h, 038Bh to 038Ah
038Fh to 038Eh
0347h to 0346h
Address
(1, 2, 3)
034Dh
Address
16. Three-Phase Motor Control Timer Function
0000h to FFFFh
Setting Range
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting Range
Indeterminate
After Reset
After Reset
1 to 15
WO
WO
RW
RW
—
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