M30625FGPGP#U9C Renesas Electronics America, M30625FGPGP#U9C Datasheet - Page 127
![IC M16C MCU FLASH 128LQFP](/photos/12/29/122943/m30625fgpgp_u9c_sml.jpg)
M30625FGPGP#U9C
Manufacturer Part Number
M30625FGPGP#U9C
Description
IC M16C MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
12.4.2
Table 12.2
NOTES:
BRK Instruction
−(Reserved)
INT3
Timer B5
Timer B4, UART1 Bus Collision Detect
Timer B3, UART0 Bus Collision Detect
SI/O4, INT5
SI/O3, INT4
UART 2 Bus Collision Detection
DMA0
DMA1
Key Input Interrupt
A/D
UART2 Transmit, NACK2
UART2 Receive, ACK2
UART0 Transmit, NACK0
UART0 Receive, ACK0
UART1 Transmit, NACK1
UART1 Receive, ACK1
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
INT1
INT2
Software Interrupt
1. Address relative to address in INTB.
2. Use the IFSR6 and IFSR7 bits in the IFSR register to select.
3. During I
4. Use the IFSR26 and IFSR27 bits in the IFSR2A register to select.
5. These interrupts cannot be disabled using the I flag.
6. Bus collision detection : During IE mode, this bus collision detection constitutes the factor of an interrupt.
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table
area. Table 12.2 lists the Relocatable Vector Tables. Setting an even address in the INTB register results in the
interrupt sequence being executed faster than in the case of odd addresses.
Jan 10, 2006
Relocatable Vector Tables
(2)
(2)
Interrupt Source
2
C mode, NACK and ACK interrupts comprise the interrupt source.
Relocatable Vector Tables
(5)
(5)
(3)
(3)
(3)
(3)
(3)
(3)
Page 110 of 390
During I
the factor of an interrupt.
(6)
(4, 6)
(4, 6)
2
C mode, however, a start condition or a stop condition detection constitutes
+104 to +107 (0068h to 006Bh)
+108 to +111 (006Ch to 006Fh)
+120 to +123 (0078h to 007Bh)
+124 to +127 (007Ch to 007Fh)
+252 to +255 (00FCh to 00FFh)
+100 to +103 (0064h to 0067h)
+112 to +115 (0070h to 0073h)
+116 to +119 (0074h to 0077h)
+128 to +131 (0080h to 0083h)
+28 to +31 (001Ch to 001Fh)
+44 to +47 (002Ch to 002Fh)
+60 to +63 (003Ch to 003Fh)
+76 to +79 (004Ch to 004Fh)
+92 to +95 (005Ch to 005Fh)
+24 to +27 (0018h to 001Bh)
+40 to +43 (0028h to 002Bh)
+48 to +51 (0030h to 0033h)
+52 to +55 (0034h to 0037h)
+56 to +59 (0038h to 003Bh)
+72 to +75 (0048h to 004Bh)
+88 to +91 (0058h to 005Bh)
+16 to +19 (0010h to 0013h)
+20 to +23 (0014h to 0017h)
+32 to +35 (0020h to 0023h)
+36 to +39 (0024h to 0027h)
+64 to +67 (0040h to 0043h)
+68 to +71 (0044h to 0047h)
+80 to +83 (0050h to 0053h)
+84 to +87 (0054h to 0057h)
+96 to +99 (0060h to 0063h)
Address (L) to Address (H)
+0 to +3 (0000h to 0003h)
Vector Address
to
(1)
Software
Interrupt
Number
1 to 3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
63
to
4
6
7
8
9
0
5
M16C/60, M16C/20
Series software manual
12.6 INT interrupt
15. Timers
15. Timers
17. Serial Interface
12.6 INT interrupt
17. Serial Interface
17. Serial Interface
14. DMAC
12.8 Key Input Interrupt
18. A/D Converter
17. Serial Interface
15. Timers
12.6 INT interrupt
M16C/60, M16C/20
Series software manual
Reference
12. Interrupt
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