M30625FGPGP#U9C Renesas Electronics America, M30625FGPGP#U9C Datasheet - Page 205
![IC M16C MCU FLASH 128LQFP](/photos/12/29/122943/m30625fgpgp_u9c_sml.jpg)
M30625FGPGP#U9C
Manufacturer Part Number
M30625FGPGP#U9C
Description
IC M16C MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.12
UARTi Special Mode Register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1
NOTES :
1. Set to “0” w hen each condition is generated.
Jan 10, 2006
UiSMR4 Register
b0
Bit Symbol
RSTAREQ
STSPSEL
STAREQ
STPREQ
U0SMR4 to U2SMR4
ACKD
ACKC
SCLHI
SWC9
Page 188 of 390
Symbol
Start Condition Generate Bit
Restart Condition Generate Bit
Stop Condition Generate Bit
SCL,SDA Output Select Bit
ACK Data Bit
ACK Data Output Enable Bit
SCL Output Stop Enable Bit
SCL Wait Bit 3
Bit Name
036Ch, 0370h, 0374h
(1)
(1)
Address
(1)
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Start and stop conditions not output
1 : Start and stop conditions output
0 : ACK
1 : NACK
0 : Serial interface data output
1 : ACK data output
0 : Disabled
1 : Enabled
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
Function
After Reset
00h
17. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW
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