MC9S12C32MFUE25 Freescale Semiconductor, MC9S12C32MFUE25 Datasheet - Page 98

• Manufacturer Part Number: MC9S12C32MFUE25
• Description: IC MCU 32K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32MFUE25

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Operating Supply Voltage: 3.3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.5.3
Read: Anytime.
Write: Anytime.
2.3.2.5.4
Read: Anytime.
Write: Anytime.
98
Module Base + 0x002A
Module Base + 0x002B
DDRJ[7:6]
RDRJ[7:6]
Reset
Reset
Field
Field
7–6
7–6
W
W
R
R
DDRJ7
RDRJ7
Data Direction Port J — This register configures port pins J[7:6] as either input or output.
DDRJ[7:6] — Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTJ
Reduced Drive Port J — This register configures the drive strength of each port J output pin as either full or
reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
0
0
7
7
Port J Data Direction Register (DDRJ)
Port J Reduced Drive Register (RDRJ)
or PTIJ registers, when changing the DDRJ register.
= Unimplemented or Reserved
= Unimplemented or Reserved
DDRJ6
RDRJ6
0
0
6
6
Figure 2-35. Port J Reduced Drive Register (RDRJ)
Figure 2-34. Port J Data Direction Register (DDRJ)
Table 2-28. DDRJ Field Descriptions
Table 2-29. RDRJ Field Descriptions
MC9S12C-Family / MC9S12GC-Family
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0
0
5
5
Rev 01.24
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0
0
4
4
Description
Description
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0
0
3
3
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—
0
0
2
2
Freescale Semiconductor
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0
0
1
1
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0
0
0
0