MC9S12C32MFUE25 Freescale Semiconductor, MC9S12C32MFUE25 Datasheet - Page 100

• Manufacturer Part Number: MC9S12C32MFUE25
• Description: IC MCU 32K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32MFUE25

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Operating Supply Voltage: 3.3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.5.7
Read: Anytime.
Write: Anytime.
2.3.2.5.8
Read: Anytime.
Write: Anytime.
100
Module Base + 0x002E
Module Base + 0x002F
PIEJ[7:6]
PIFJ[7:6]
Reset
Reset
Field
Field
7–6
7–6
W
W
R
R
PIEJ7
PIFJ7
Interrupt Enable Port J — This register disables or enables on a per pin basis the edge sensitive external
interrupt associated with port J.
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Interrupt Flags Port J — Each flag is set by an active edge on the associated input pin. This could be a rising
or a falling edge based on the state of the PPSJ register. To clear this flag, write “1” to the corresponding bit in
the PIFJ register. Writing a “0” has no effect.
0 No active edge pending.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a “0” has no effect.
Writing a “1” clears the associated flag.
Port J Interrupt Enable Register (PIEJ)
Port J Interrupt Flag Register (PIFJ)
= Unimplemented or Reserved
= Unimplemented or Reserved
PIEJ6
PIFJ6
0
0
6
6
Figure 2-38. Port J Interrupt Enable Register (PIEJ)
Figure 2-39. Port J Interrupt Flag Register (PIFJ)
Table 2-32. PIEJ Field Descriptions
Table 2-33. PIFJ Field Descriptions
MC9S12C-Family / MC9S12GC-Family
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Rev 01.24
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Description
Description
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3
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2
Freescale Semiconductor
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