MC9S12C32MFUE25 Freescale Semiconductor, MC9S12C32MFUE25 Datasheet - Page 195

• Manufacturer Part Number: MC9S12C32MFUE25
• Description: IC MCU 32K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32MFUE25

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Operating Supply Voltage: 3.3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.2
The DBG sub-module relies on the external bus interface (generally the MEBI) when the DBG is matching
on the external bus.
The tag pins in
Freescale Semiconductor
PE3/LSTRB/ TAGLO
BKGD/MODC/
CPU PROGRAM COUNTER
INSTRUCTION
Pin Name
LAST CYCLE
BUS CLOCK
TAGHI
External Signal Description
WRITE DATA BUS
READ DATA BUS
ADDRESS BUS
WRITE DATA BUS
READ DATA BUS
READ/WRITE
DBG MODE ENABLE
CHANGE-OF-FLOW
INDICATORS
MCU IN BDM
DBG READ DATA BUS
Table 7-1
READ/WRITE
REGISTER
Pin Functions
Table 7-1. External System Pins Associated with DBG and MEBI
TAGLO
TAGHI
(part of the MEBI) may also be a part of the breakpoint operation.
Figure 7-2. DBG Block Diagram in DBG Mode
M
U
X
When instruction tagging is on, a 0 at the falling edge of E tags the high half of the
instruction word being read into the instruction queue.
In expanded wide mode or emulation narrow modes, when instruction tagging is on
and low strobe is enabled, a 0 at the falling edge of E tags the low half of the
instruction word being read into the instruction queue.
MC9S12C-Family / MC9S12GC-Family
M
U
X
INSTRUCTION
ADDRESS/DATA/CONTROL
ADDRESS
M
U
X
COMPARATOR A
COMPARATOR B
COMPARATOR C
LAST
REGISTERS
Rev 01.24
64 x 16 BIT
REGISTER
CAPTURE
PROFILE
BUFFER
TRACE
WORD
Chapter 7 Debug Module (DBGV1) Block Description
Description
CONTROL
MATCH_A
MATCH_B
MATCH_C
LOOP1
EVENT ONLY
POINTER
M
U
X
STORE
DETAIL
PROFILE CAPTURE MODE
CONTROL
TRACER
OR PROFILING DATA
BUFFER
LOGIC
TRACE BUFFER
TAG
FORCE
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