Z8F0123SB005EG Zilog, Z8F0123SB005EG Datasheet - Page 172

• Manufacturer Part Number: Z8F0123SB005EG
• Description: IC ENCORE MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0123SB005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 269-3757

Table 99. OCD Control Register (OCDCTL)
.
BITS
FIELD
RESET
R/W
PS024314-0308
DBGMODE
R/W
7
0
A reset and stop function can be achieved by writing
function can be achieved by writing
a run function can be implemented by writing
DBGMODE—DEBUG Mode
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = Z8 Encore! XP F0823 Series device is operating in NORMAL mode
1 = Z8 Encore! XP F0823 Series device is in DEBUG mode
BRKEN—Breakpoint Enable
This bit controls the behavior of the
are disabled and the
when a
cally set to 1.
0 = Breakpoints are disabled
1 = Breakpoints are enabled
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (
0 = Debug Acknowledge is disabled
1 = Debug Acknowledge is enabled
Reserved—0 when read
RST—Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the OCD is not reset. This bit is auto-
matically cleared to 0 at the end of reset.
0 = No effect
1 = Reset the Flash Read Protect Option Bit device
BRK
BRKEN
R/W
6
0
instruction is decoded, the
DBGACK
BRK
R/W
5
0
instruction behaves similar to an
BRK
instruction is decoded and breakpoints are enabled. If the
FFH
R
4
0
BRK
41H
) to the host when a Breakpoint occurs.
DBGMODE
instruction (opcode
to this register. If the device is in DEBUG mode,
40H
R
3
0
bit of the OCDCTL register is automati-
Reserved
to this register.
81H
Z8 Encore! XP
to this register. A reset and go
NOP
R
2
0
00H
instruction. If this bit is 1,
Product Specification
). By default, breakpoints
R
1
0
®
On-Chip Debugger
F0823 Series
RST
R/W
0
0
162