EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 51

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

DS785UM1
2.3.3 APB Slave
2.3.4 Register Definitions
An APB Slave responds to accesses initiated by bus masters. The slave uses signals from
the decoder to determine when it should respond to a bus access. All other signals required
for the access, such as the address and control information, are generated by the AHB-to-
APB Bridge.
The ARM920T Core has thirty seven 32-bit internal registers, where some are modal and
some are banked. If operating in Thumb instructions state, the ARM Core must switch to
ARM instructions state before taking an exception. The return instruction will restore the ARM
Core to the Thumb state. Most tasks are executed out of User mode. The ARM920T Core’s
operating modes are shown in
Table 2-5
will bank or store a specific number of registers. Banked register information is not shared
between modes. FIQs bank the largest number of registers, and increase performance by
reducing the need to push/pop registers from the stack.
Note: Due to decoding optimization, the APB peripheral registers are aliased throughout each
peripherals register bank. Do not attemp to access an unspecified register within the bank.
illustrates the use of all registers for the ARM920T Core’s operating modes. Each
Supervisor
System
Mode
Abort:
Undef
User
IRQ
FIQ
Table 2-4. ARM920T Core Operating Modes
Copyright 2007 Cirrus Logic
Table
2-4.
Unprivileged normal operating mode
Fast interrupt (high priority) mode when FIQ is
asserted
Interrupt request (normal) mode when IRQ is
asserted
Software interrupt instruction (SWI) or reset will
cause entry into this mode.
Memory access violation will cause entry into this
mode.
Undefined instructions mode
Privileged mode. Uses same registers as User
mode
ARM920T Core and Advanced High-Speed Bus (AHB)
Description
EP93xx User’s Guide
2-13
2