EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 407

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

DS785UM1
10.1.10.2.3 DMA_BUF_NEXT
10.1.10.3 Data Transfer Initiation
(which BCRx is free can be determined using the STATUS.Nextbuffer status bit - see
“STATUS” on page
When the DMA Buffer FSM transitions from DMA_BUF_ON to DMA_NO_BUF state due to
end of buffer, the DONE status bit is asserted and the DONE interrupt is set if enabled. The
TC (Terminal Count) output is asserted by the DMA to the external device if the BCR register
has expired for the current buffer (when in external DMA transfer mode and TC is
programmed as an output signal from the DMA). The end of buffer can also be due to receipt
of a DEOT input from the external device (when in external DMA transfer mode and DEOT is
configured as an input signal to the DMA). The TCS and EOTS status bits of the STATUS
register indicate what caused the end of buffer.
The DMA Buffer FSM enters the DMA_BUF_NEXT state from the DMA_BUF_ON state when
a write occurs to the second of the BCRx registers (that is, the BCRx register that was not
written to when in the DMA_NO_BUF state).
The DMA Buffer FSM stays in this state until the transfer using the active buffer has ended,
either as a result of BCRx reaching zero or due to receipt of a DEOT input from the external
device (when in external DMA transfer mode and DEOT is configured as an input signal to
the DMA). The TCS and EOTS status bits of the STATUS register indicate what caused the
end of buffer.
Data transfers to/from memory or external device can occur in the DMA_BUF_NEXT state.
When the DMA Buffer FSM transitions from DMA_BUF_NEXT to DMA_BUF_ON state as a
result of the BCR count expiring, the TC (Terminal Count) output is asserted by the DMA to
the external device to indicate that the BCR register has expired for the current buffer (when
in external DMA transfer mode and TC is programmed as an output signal from the DMA).
When the DMA Buffer FSM transitions from DMA_BUF_NEXT to DMA_BUF_ON state, the
NFB (Next Frame Buffer) interrupt is generated (if enabled). This signals that one of the
buffer descriptors is now free for update. For example the following sequence of events could
occur:
Memory-to-memory transfers require a read-from and a write-to memory to complete each
transfer.
• BCR0 is programmed => move to DMA_BUF_ON state.
• BCR1 is programmed => move to DMA_BUF_NEXT state.
• Channel is enabled => transfers begin using Buffer0.
• Buffer0 transfer ends => move to DMA_BUF_ON state and begin transfers with Buffer1.
• NFB interrupt is generated when FSM moves to DMA_BUF_ON state, signalling that
• Buffer0 is now free for update.
10-37).
Copyright 2007 Cirrus Logic
EP93xx User’s Guide
DMA Controller
10-13
10