EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 254

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

7
CursorBlinkRateCtrl
7-72
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_0224
Default: 0x0000_0000
Definition: Blink Rate Control register
Bit Descriptions:
30
14
29
13
RSVD
28
12
RSVD:
EN:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
When Dual Scan mode is enabled by writing DSCAN = ‘1’
in the
this field specifies the starting vertical Y location (in the
lower half of the display) of the cursor image. The value is
compared to the vertical line counter and it should be
specified to be between the active start and active stop
vertical line values.
The cursor hardware will clip the cursor at the bottom of
the display. To prevent cursor distortion, a new Y Location
value will not be used until the next frame.
Reserved - Unknown during read
Enable - Read/Write
Writing a ‘1’ to this bit enables hardware cursor blinking
and enables the blink rate counter. Writing a ‘0’ to this bit
disables hardware cursor blinking and disables the blink
rate counter:
0 - Hardware cursor blinking not enabled
1 - Hardware cursor blinking enabled
When EN = ‘1’ and the 2-bit cursor pixel fetched from
SDRAM is ‘10’,
the blink toggle and
of the blink toggle.
When EN = ‘1’ and the 2-bit cursor pixel fetched from
SDRAM is ‘11’,
of the blink toggle and
part of the blink toggle.
EN
24
8
PixelMode
RSVD
23
7
CursorBlinkColor1,
CursorColor2,
register, the Y Location value written to
22
6
CursorColor1,
CursorColor1,
21
5
20
4
is used for the ‘on’ part of
RATE
is used for the ‘off’ part
is used for the ‘on’ part
19
3
is used for the ‘off’
18
2
17
1
DS785UM1
16
0