EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 308

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

9
9-6
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
Complete state. Thus, the Carrier Deference state may be entered and exited immediately, or
there may be a delay depending on the state when entered.
When CRS becomes active, the Line Busy state is entered. This state is held until CRS
returns to clear which starts the IFG timer. The time-out process after CRS clears is called
Carrier Deference. In the MAC, Carrier Deference has two options as selected by the bit 2-
part DefDis (TXCtl). If 2-part DefDis is clear, the two part deferral is used which meets the
requirements of ISO/IEC 8802-3 paragraph 4.2.3.2.1. As shown in the diagram, if CRS
becomes active during the first 2/3 (6.4 μsec) of the IFG, the MAC restarts the IFG timer. If
CRS becomes active during the last 1/3 of the IFG, the timer is not restarted to ensure fair
access to the medium.
If 2-part DefDis is set, the two part deferral is disabled. In this option, the IFG timer is allowed
to complete even if CRS becomes active after the timer has started.
The 2-part deferral has an advantage for AUI connections to either 10BASE-2 or 10BASE-5.
If the deferral process simply allowed the IFG timer to complete, then it is possible for a short
Inter Frame Gap to be generated. The 2-part deferral prevents short IFGs. The disadvantage
of the 2-part deferral is longer deferrals. In 10BASE-T systems, either deferral method should
operate about the same.
complete
NOTES:
2. There is logic to maintain the 9.6 usec
IFG spacing between back-to-back
transmitted packets.
That logic is not shown.
1. In this diagram, FDX (TestCTL) is clear.
Timer
IFG Delay
9.6 usec
Fixed
No two-part deferral
[2-part DefDis set]
CRS changes
from 1 to 0
When this Carrier Deference state diagram is entered from the Packet
Transmission Process, the entry may be to any state shown. The Packet
Transmission Process exits this state diagram ONLY from IFG Complete.
Figure 9-4. Carrier Deference State Diagram
CRS changes
from 1 to 0
Copyright 2007 Cirrus Logic
[wait for CRS to clear]
complete
Timer
IFG Complete
Line Busy
6.4 usec
[2/3 IFG]
3.2 usec
[1/3 IFG]
Delay
Fixed
Delay
Two-part deferral used
[2-part DefDis clear]
CRS changes
from 0 to 1
Timer complete
If CRS goes to 1 during
the 6.4 usec timer, go back
to the Line Busy state.
CRS is Carrier Sense
The control bit 2-partDefDis
selects two-part deferral when
clear, and disables two-part
when set.
DS785UM1