ATMEGA644-20PU Atmel, ATMEGA644-20PU Datasheet - Page 96
![IC AVR MCU FLASH 64K 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA644-20PU
Manufacturer Part Number
ATMEGA644-20PU
Description
IC AVR MCU FLASH 64K 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA644-20PU
Manufacturer:
Atmel
Quantity:
1 930
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96
ATmega644
Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f
Figure 13-10
mode and PWM mode, where OCR0A is TOP.
Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
Figure 13-11
PWM mode where OCR0A is TOP.
Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
TCNTn
TCNTn
TCNTn
(clk
(clk
(clk
OCRnx
OCRnx
TOVn
OCFnx
(CTC)
OCFnx
clk
clk
clk
clk
clk
clk
I/O
I/O
I/O
I/O
I/O
I/O
Tn
Tn
Tn
/8)
/8)
/8)
shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
caler (f
clk_I/O
OCRnx - 1
MAX - 1
TOP - 1
/8)
OCRnx
MAX
TOP
OCRnx Value
TOP
OCRnx + 1
BOTTOM
BOTTOM
clk_I/O
/8)
BOTTOM + 1
BOTTOM + 1
OCRnx + 2
clk_I/O
2593N–AVR–07/10
/8)
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