ATMEGA644-20PU Atmel, ATMEGA644-20PU Datasheet - Page 292
ATMEGA644-20PU
Manufacturer Part Number
ATMEGA644-20PU
Description
IC AVR MCU FLASH 64K 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644-20PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA644-20PU
Manufacturer:
Atmel
Quantity:
1 930
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ATmega644
Programming the EEPROM
K. End Page Programming
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are
Figure 25-2. Addressing the Flash Which is Organized in Pages
Note:
Figure 25-3. Programming the Flash Waveforms
Note:
The EEPROM is organized in pages, see
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
reset.
RESET +12V
RDY/BSY
PAGEL
XTAL1
DATA
1. PCPAGE and PCWORD are listed in
1. “XX” is don’t care. The letters refer to the programming description above.
XA1
XA0
BS1
BS2
WR
OE
PROGRAM MEMORY
0x10
PROGRAM
COUNTER
A
PAGE
ADDR. LOW
PAGE ADDRESS
WITHIN THE FLASH
B
PCMSB
DATA LOW
C
PCPAGE
DATA HIGH
D
XX
E
ADDR. LOW
B
PAGEMSB
Table 25-8 on page
PCWORD
Table 25-7 on page
DATA LOW
C
WORD ADDRESS
WITHIN A PAGE
(1)
F
DATA HIGH
D
INSTRUCTION WORD
XX
E
PAGE
ADDR. HIGH
287.
G
(1)
287. When programming the
ADDR. EXT.H
H
I
XX
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
2593N–AVR–07/10
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