ATMEGA644-20PU Atmel, ATMEGA644-20PU Datasheet - Page 373

• Manufacturer Part Number: ATMEGA644-20PU
• Description: IC AVR MCU FLASH 64K 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644-20PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2593N–AVR–07/10
23 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 259
24 Boot Loader Support – Read-While-Write Self-Programming ......... 269
25 Memory Programming ......................................................................... 283
26 Electrical Characteristics .................................................................... 315
22.7On-chip Debug Related Register in I/O Memory .................................................258
22.8Using the JTAG Programming Capabilities .........................................................258
22.9Bibliography .........................................................................................................258
23.1Features ..............................................................................................................259
23.2System Overview ................................................................................................259
23.3Data Registers .....................................................................................................259
23.4Boundary-scan Specific JTAG Instructions .........................................................261
23.5Boundary-scan Related Register in I/O Memory .................................................262
23.6Boundary-scan Chain ..........................................................................................263
23.7ATmega644 Boundary-scan Order .....................................................................266
23.8Boundary-scan Description Language Files ........................................................268
24.1Boot Loader Features ..........................................................................................269
24.2Application and Boot Loader Flash Sections .......................................................269
24.3Read-While-Write and No Read-While-Write Flash Sections ..............................270
24.4Boot Loader Lock Bits .........................................................................................272
24.5Entering the Boot Loader Program ......................................................................273
24.6Addressing the Flash During Self-Programming .................................................275
24.7Self-Programming the Flash ................................................................................276
25.1Program And Data Memory Lock Bits .................................................................283
25.2Fuse Bits .............................................................................................................284
25.3Signature Bytes ...................................................................................................286
25.4Calibration Byte ...................................................................................................286
25.5Page Size ............................................................................................................286
25.6Parallel Programming Parameters, Pin Mapping, and Commands .....................286
25.7Parallel Programming ..........................................................................................288
25.8Serial Downloading .............................................................................................298
25.9Serial Programming Instruction set .....................................................................300
25.10Programming via the JTAG Interface ................................................................302
26.1Absolute Maximum Ratings* ...............................................................................315
26.2DC Characteristics ..............................................................................................315
26.3External Clock Drive Waveforms .........................................................................317
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