ATMEGA644-20PU Atmel, ATMEGA644-20PU Datasheet - Page 372

• Manufacturer Part Number: ATMEGA644-20PU
• Description: IC AVR MCU FLASH 64K 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644-20PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

iv
ATmega644
19 2-wire Serial Interface .......................................................................... 200
20 Analog Comparator ............................................................................. 230
21 Analog-to-digital Converter ................................................................ 233
22 JTAG Interface and On-chip Debug System ..................................... 253
18.1Overview .............................................................................................................191
18.2Clock Generation .................................................................................................191
18.3SPI Data Modes and Timing ...............................................................................192
18.4Frame Formats ....................................................................................................192
18.5Data Transfer ......................................................................................................194
18.6USART MSPIM Register Description ..................................................................196
18.7AVR USART MSPIM vs.
19.1Features ..............................................................................................................200
19.22-wire Serial Interface Bus Definition ..................................................................200
19.3Data Transfer and Frame Format ........................................................................201
19.4Multi-master Bus Systems, Arbitration and Synchronization ...............................204
19.5Overview of the TWI Module ...............................................................................206
19.6Using the TWI ......................................................................................................208
19.7Transmission Modes ...........................................................................................211
19.8Multi-master Systems and Arbitration ..................................................................224
19.9TWI Register Description ....................................................................................225
20.1Analog Comparator Multiplexed Input .................................................................232
21.1Features ..............................................................................................................233
21.2Operation .............................................................................................................234
21.3Starting a Conversion ..........................................................................................235
21.4Prescaling and Conversion Timing ......................................................................236
21.5Changing Channel or Reference Selection .........................................................239
21.6ADC Noise Canceler ...........................................................................................241
21.7ADC Conversion Result ......................................................................................246
22.1Overview .............................................................................................................253
22.2TAP – Test Access Port ......................................................................................253
22.3TAP Controller .....................................................................................................255
22.4Using the Boundary-scan Chain ..........................................................................256
22.5Using the On-chip Debug System .......................................................................256
22.6On-chip Debug Specific JTAG Instructions .........................................................257
AVR SPI 199
2593N–AVR–07/10