SAK-C161CS-LF CA Infineon Technologies, SAK-C161CS-LF CA Datasheet - Page 62
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SAK-C161CS-LF CA
Manufacturer Part Number
SAK-C161CS-LF CA
Description
IC MCU 16BIT 256KB TQFP-128-2
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAK-C161CS-LF_CA.pdf
(89 pages)
Specifications of SAK-C161CS-LF CA
Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
93
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
128-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
K161CSLFCANP
K161CSLFCAXT
SAK-C161CS-LFCA
SAK-C161CS-LFCAINTR
SAK-C161CS-LFCATR
SAK-C161CS-LFCATR
SAKC161CSLFCAXT
SP000106869
K161CSLFCAXT
SAK-C161CS-LFCA
SAK-C161CS-LFCAINTR
SAK-C161CS-LFCATR
SAK-C161CS-LFCATR
SAKC161CSLFCAXT
SP000106869
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
For a period of
deviation D
where
So for a period of 3 TCLs @ 25 MHz (i.e.
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse
train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL
jitter is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Figure 12
Data Sheet
Max. jitter
±26.5
(
N
N
±30
±20
±10
= number of consecutive TCLs
±1
D
ns
N
N
min
TCL)
:
1
Approximated Maximum Accumulated PLL Jitter
= 3TCL
This approximated formula is valid for
1
min
N
< –
N
=
TCL the minimum value is computed using the corresponding
< –
NOM
N
40 and 10 MHz
10
TCL
- 1.288 ns = 58.7 ns (@
NOM
- D
< –
Figure
f
CPU
N
20
< –
N
58
D
and 1
25 MHz.
= 3): D
12).
N
[ns] = (13.3 +
3
N
f
CPU
= (13.3 +
30
40.
= 25 MHz).
N
3
C161CS/JC/JI-32R
6.3) /
6.3) / 25 = 1.288 ns,
C161CS/JC/JI-L
40
f
CPU
V3.0, 2001-01
Figure
[MHz],
MCD04455
10 MHz
16 MHz
20 MHz
25 MHz
12).
N