SAK-C161CS-LF CA Infineon Technologies, SAK-C161CS-LF CA Datasheet - Page 61

• Manufacturer Part Number: SAK-C161CS-LF CA
• Description: IC MCU 16BIT 256KB TQFP-128-2
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C161CS-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 93
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 128-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: K161CSLFCANP; K161CSLFCAXT; SAK-C161CS-LFCA; SAK-C161CS-LFCAINTR; SAK-C161CS-LFCATR; SAK-C161CS-LFCATR; SAKC161CSLFCAXT; SP000106869

P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 10
generation mode.
Table 10
CLKCFG
(P0H.7-5)
1)
2)
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
(i.e. the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
f
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
Data Sheet
CPU
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
The external clock input range refers to a CPU clock range of 10 … 25 MHz.
The maximum frequency depends on the duty cycle of the external clock signal.
=
f
OSC
associates the combinations of these three bits with the respective clock
CPU Frequency
f
f
f
f
f
f
f
f
f
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
CPU
F). With every F’th transition of
C161CS/JC/JI Clock Generation Modes
f
OSC
f
=
/ 2
CPU
. The slight variation causes a jitter of
4
3
2
5
1
1.5
2.5
f
OSC
is half the frequency of
F
f
OSC
6.66 to 16.6 MHz
4 to 10 MHz
External Clock
Input Range
2.5 to 6.25 MHz
3.33 to 8.33 MHz
5 to 12.5 MHz
2 to 5 MHz
1 to 25 MHz
2 to 50 MHz
for any TCL.
57
1)
f
OSC
f
OSC
the PLL circuit synchronizes the CPU
and the high and low time of
Notes
Default configuration
–
–
–
Direct drive
–
CPU clock via prescaler
–
B
) the CPU clock is derived from
f
CPU
f
CPU
is constantly adjusted so
2)
which also effects the
C161CS/JC/JI-32R
C161CS/JC/JI-L
V3.0, 2001-01
f
OSC
f
CPU
.