SAK-C161CS-LF CA Infineon Technologies, SAK-C161CS-LF CA Datasheet - Page 40

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SAK-C161CS-LF CA

Manufacturer Part Number
SAK-C161CS-LF CA
Description
IC MCU 16BIT 256KB TQFP-128-2
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAK-C161CS-LF CA

Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
93
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
128-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
K161CSLFCANP
K161CSLFCAXT
SAK-C161CS-LFCA
SAK-C161CS-LFCAINTR
SAK-C161CS-LFCATR
SAK-C161CS-LFCATR
SAKC161CSLFCAXT
SP000106869
Power Management
The C161CS/JC/JI provides several means to control the power it consumes either at a
given time or averaged over a certain timespan. Three mechanisms can be used (partly
in parallel):
• Power Saving Modes switch the C161CS/JC/JI into a special operating mode
• Clock Generation Management controls the distribution and the frequency of
• Peripheral Management permits temporary disabling of peripheral modules (control
The on-chip RTC supports intermittend operation of the C161CS/JC/JI by generating
cyclic wakeup signals. This offers full performance to quickly react on action requests
while the intermittend sleep phases greatly reduce the average power consumption of
the system.
Data Sheet
(control via instructions).
Idle Mode stops the CPU while the peripherals can continue to operate.
Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may
optionally continue running). Sleep Mode can be terminated by external interrupt
signals.
internal and external clock signals (control via register SYSCON2).
Slow Down Mode lets the C161CS/JC/JI run at a CPU clock frequency of
1 … 32 (half for prescaler operation) which drastically reduces the consumed power.
The PLL can be optionally disabled while operating in Slow Down Mode.
External circuitry can be controlled via the programmable frequency output FOUT.
via register SYSCON3).
Each peripheral can separately be disabled/enabled. A group control option disables
a major part of the peripheral set by setting one single bit.
36
C161CS/JC/JI-32R
C161CS/JC/JI-L
V3.0, 2001-01
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