MC68331CEH16 Freescale Semiconductor, MC68331CEH16 Datasheet - Page 62

• Manufacturer Part Number: MC68331CEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Device Core: ColdFire
• Family Name: 68K/M683xx
• Maximum Speed: 16 MHz
• Ram Size: 80 Byte
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 18
• Interface Type: QSPI/SCI/UART
• Number Of Timers: 1
• Processor Series: M683xx
• Core: CPU32
• Eeprom Memory: 0 Bytes
• Input Output: 18
• Interface: EBI/EMI, SCI, SPI, UART/USART
• Ios: 18
• Memory Type: ROMless
• Number Of Bits: 32
• Package Type: 132-pin QFP
• Programmable Memory: 0 Bytes
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 16MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 80 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

HALT — Halt
SPSR — QSPI Status Register
SPIF — QSPI Finished Flag
MODF — Mode Fault Flag
HALTA — Halt Acknowledge Flag
Bit 4 — Not Implemented
CPTQP — Completed Queue Pointer
5.4.3 QSPI RAM
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15
When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can
later be restarted.
SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU
reads this register to obtain status information and writes it to clear status flags.
SPIF is set after execution of the command at the address in ENDQP.
The QSPI asserts MODF when the QSPI is the serial master (MSTR = 1) and the SS input pin is negat-
ed by an external driver.
HALTA is asserted when the QSPI halts in response to CPU assertion of HALT.
CPTQP points to the last command executed. It is updated when the current command is complete.
When the first command in a queue is executing, CPTQP contains either the reset value ($0) or a point-
er to the last command completed in the previous queue.
The QSPI contains an 80-byte block of dual-access static RAM that is used by both the QSPI and the
CPU. The RAM is divided into three segments: receive data, transmit data, and command control data.
Receive data is information received from a serial device external to the MCU. Transmit data is infor-
mation stored by the CPU for transmission to an external peripheral. Command control data is used to
perform the transfer.
Refer to the following illustration of the organization of the RAM.
0 = Halt not enabled
1 = Halt enabled
0 = QSPI not finished
1 = QSPI finished
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the QSPI was enabled
0 = QSPI not halted
1 = QSPI halted
in master mode (SS input taken low).
SPCR3
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
8
SPIF
7
0
RESET:
MODF
6
0
HALTA
5
0
4
0
0
3
0
0
CPTQP
MC68331TS/D
$YFFC1F
0
0
0