MC68331CEH16 Freescale Semiconductor, MC68331CEH16 Datasheet - Page 49

• Manufacturer Part Number: MC68331CEH16
• Description: IC MCU 32BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Device Core: ColdFire
• Family Name: 68K/M683xx
• Maximum Speed: 16 MHz
• Ram Size: 80 Byte
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 18
• Interface Type: QSPI/SCI/UART
• Number Of Timers: 1
• Processor Series: M683xx
• Core: CPU32
• Eeprom Memory: 0 Bytes
• Input Output: 18
• Interface: EBI/EMI, SCI, SPI, UART/USART
• Ios: 18
• Memory Type: ROMless
• Number Of Bits: 32
• Package Type: 132-pin QFP
• Programmable Memory: 0 Bytes
• Voltage, Range: 4.5-5.5 V
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 16MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 80 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68331TS/D
TBLSN/TBLUN
1. Privileged instruction.
TBLS/TBLU
Instruction
TRAPcc
TRAPV
SWAP
SUBQ
SUBA
SUBX
TRAP
UNLK
SUBI
SUB
TAS
TST
#<data>, <ea>
#<data>, <ea>
Dym : Dyn, Dn
Dym : Dyn, Dn
(An),
<ea>, Dn
Dn, <ea>
<ea>, An
<ea>, Dn
<ea>, Dn
#<data>
#<data>
Syntax
Dn, Dn
<ea>
none
none
<ea>
Freescale Semiconductor, Inc.
Table 20 Instruction Set Summary (Continued)
Dn
An
For More Information On This Product,
(An)
Go to: www.freescale.com
Operand Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
16, 32
none
none
none
16
32
8
Destination
Destination
Destination
Destination
Destination
Destination Tested Condition Codes bit 7 of
Destination
Dyn
(Temp
(Dym
Dyn
(Temp
Dym
SSP
SSP
vector address
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Source
An
SP; (SP)
Dym
Dym
2
4
Temp
256)
Dn [7 : 0])
Dn [7 : 0]) / 256
0, to set condition codes
SSP; format/vector offset
SSP; PC
Source
Source
Data
Data
Source
Temp
Temp
Temp
Dn
PC
An, SP
MSW
Operation
Destination
Destination
Temp
X
Dn
(SSP); SR
Destination
Destination
Temp
4
Destination
LSW
SP
(SSP);
(SSP);
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