DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 460

IC H8S/2300 MCU FLASH 144QFP

DF2338VFC25V

Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2338VFC25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF
PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port F Register (PORTF)
Note: * Determined by state of pins PF
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as
PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.
Rev.4.00 Sep. 07, 2007 Page 428 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
PF7DR
R/W
PF7
— *
R
7
0
7
PF6DR
R/W
PF6
— *
R
6
0
6
7
to PF
7
PF5DR
to PF
R/W
PF5
— *
0
R
5
0
5
) must always be performed on PFDR.
0
.
PF4DR
R/W
PF4
— *
R
4
0
4
PF3DR
R/W
PF3
— *
R
0
3
3
PF2DR
R/W
PF2
— *
R
2
0
2
PF1DR
R/W
PF1
— *
R
1
0
1
7
to PF
PF0DR
R/W
PF0
— *
R
0
0
0
0
).

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