DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 269

IC H8S/2300 MCU FLASH 144QFP

DF2338VFC25V

Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2338VFC25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.4.2
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC
transfer end pin output. A port can be set for output automatically, and a transfer end signal
output, by setting the appropriate bit.
DMATCR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.
Bit 5
TEE1
0
1
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.
Bit 4
TEE0
0
1
The TEND pins are assigned only to channel B in short address mode.
The transfer end signal indicates the transfer cycle in which the transfer counter reached 0,
regardless of the transfer source. An exception is block transfer mode, in which the transfer end
signal indicates the transfer cycle in which the block counter reached 0.
Bits 3 to 0—Reserved: Read-only bits, always read as 0.
Bit
Initial value :
R/W
DMA Terminal Control Register (DMATCR)
Description
TEND1 pin output disabled
TEND1 pin output enabled
Description
TEND0 pin output disabled
TEND0 pin output enabled
:
:
7
0
6
0
TEE1
R/W
5
0
TEE0
R/W
0
4
Rev.4.00 Sep. 07, 2007 Page 237 of 1210
3
0
2
0
REJ09B0245-0400
1
0
(Initial value)
(Initial value)
0
0

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