DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 10

• Manufacturer Part Number: DF2338VFC25V
• Description: IC H8S/2300 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2338VFC25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
6.3.5 Chip Select
Signals
Section 13 Watchdog
Timer
14.2.8 Bit Rate
Register (BRR)
Table 14.3 BRR
Settings for Various Bit
Rates (Asynchronous
Mode)
19.4.1 Features
Rev.4.00 Sep. 07, 2007 Page viii of xxx
Page
153
579 to 594 Note shown below deleted
616
738
Revision (See Manual for Details)
Description amended
…Enabling or disabling of CS
setting the data direction register (DDR) bit for the port
corresponding to the particular CS
(CS/67E), and the CS25 enable bit (CS25E).
In expanded mode with on-chip ROM disabled, the CS
placed in the output state after a reset. Pins CS
placed in the input state after a reset, so the corresponding
DDR bits as well as bits CS/67E and CS25E should be set to 1
when outputting signals CS
In expanded mode with on-chip ROM enabled, pins CS
are all placed in the input state after a reset, so the
corresponding DDR bits as well as bits CS/67E and CS25E
should be set to 1 when outputting signals CS
details, …
Note: The WDTOVF pin function cannot be used in the F-ZTAT
Table 14.3 amended
Description amended
•
The flash memory can be reprogrammed min. 100 times.
Reprogramming capability
version.
Bit Rate
(bits/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
1
n
3
3
2
2
1
1
0
0
0
0
0
to CS
n
signal output is performed by
φ φ = 25 MHz
110
80
162
80
162
80
162
80
40
24
19
N
n
7
.
pin, the CS/67 enable bit
Error
(%)
–0.02
0.47
–0.15
0.47
–0.15
0.47
–0.15
0.47
–0.76
1.00
1.73
1
1
to CS
to CS
7
. For
0
7
0
are
pin is
to CS
7