MC908JB16DWE Freescale Semiconductor, MC908JB16DWE Datasheet - Page 260

• Manufacturer Part Number: MC908JB16DWE
• Description: IC MCU 16K FLASH 6MHZ USB 28SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB16DWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SCI/SPI/USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 384Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clock Generator Module (CGM)
13.9.6 Phase Detector Control Register (PDCR)
13.10 Pre-Defined VCO Output Frequency Settings
Technical Data
260
Frequency
Channel
(MHz)
26.54
26.59
26.64
26.69
26.74
Frequency
Crystal
(MHz)
12
12
12
12
12
Table 13-1. Predefined Programming Setting for PLL
Address:
Reset:
The phase detector control register configures the phase detector for
both PLLs.
PHD_[7:0] — Phase detector Control Bits for both PLLs
The exact frequency values for the following required channels cannot
be synthesized by using a reference frequency higher than 10kHz. An
absolute offset frequency from +1.66kHz to +1.89kHz will be introduced
for different channels and the maximum relative offset is only ±115Hz
with 1.775kHz as the center point (see
Programming Setting for
further minimized by reducing the crystal frequency by 60 ppm (360Hz)
in actual application.
Read:
Write:
Set PHD_[7:0] = $70 for maximum performance.
Figure 13-14. Phase Detector Control Register (PDCR)
Divider R
PHD_7
$0059
Bit 7
1
288
338
268
370
302
Clock Generator Module (CGM)
PHD_6
6
0
Frequency
Reference
41.67
35.50
44.78
32.43
39.74
(kHz)
PHD_5
5
0
PLL). The absolute offset frequency can be
PHD_4
Divider N
4
1
637
749
595
823
673
Table 13-1 . Predefined
PHD_3
3
0
Frequency
MC68HC908JB16
26.54166
26.59171
26.64179
26.69189
26.74172
PHD_2
(MHz)
VCO
Freescale Semiconductor
2
0
PHD_1
1
0
Absolute
Offset
+1.66
+1.71
+1.79
+1.89
+1.72
(kHz)
—
Rev. 1.1
PHD_0
Bit 0
0