ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 417

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

KNOWN LIMITATIONS (Cont’d)
T
Figure 4. Critical Window Timing Diagram
Figure 5. Reception of a Sequence of Frames
Side-effect of Workround 1
Because the while loop lasts 16 CPU cycles, if
f
miss a dominant state on the bus if it lasts just one
CAN bit time and the bus speed is high enough
(see
Table 75. While Loop Timing
Note: As can be seen from the above table, no
side effect occurs in cases when f
higher and if the CAN baud rate is below 1MBaud.
CPU
CAN frame
FMP
BUS
CPU
24 MHz
16 MHz
8 MHz
4 MHz
≤16MHz at high baud rate, it is possible to
Table
f
f
CPU
CPU
: This is minimum CAN frame duration
75)
T
CAN frame
Baud rate for possible
No dominant bit missed
missed dominant bit
0
> f
> 500 kHz
> 250 kHz
1 MBaud
1
Acknowledge: last
dominant bit in the frame
CPU
/ 16
CPU
Time to test RX pin and to
release the FIFO 4.5 µs@4MHz Time between the end of the
is 16MHz or
T
T
IT disable
CAN frame
CAN Frame
1
ST92F124/F150/F250 - KNOWN LIMITATIONS
If this happens, we will continue waiting in the
while loop instead of releasing the FIFO immedi-
ately. The workaround is still valid because we will
not release the FIFO during the critical period. But
the application may lose additional time waiting in
the while loop as we are no longer able to guar-
antee a maximum of 6 CAN bit times spent in the
workaround.
In this particular case the time the application can
spend in the workaround may increase up to a full
CAN frame, depending of the frame contents. This
case is very rare but happens when a specific se-
quence is present on in the CAN frame.
The example in
is 12/f
If the application is using the maximum baud rate
and the possible delay caused by the workaround
is not acceptable, there is another workaround
which reduces the Rx pin sampling time.
2
CPU
T
IT higher level
acknowledge and the critical windows
- 6 full CAN bit times+ time to the sample point
approx. 13µs @ 500kBd
and the sampling time is 16/f
Critical window: the received
message is placed in the FIFO
Figure 6
T
CAN frame
2
T
shows reception if TCAN
IT CAN
3
A release is not
allowed at this time
CPU
2
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