ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 273

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

I
10.8.7 Register Description
IMPORTANT:
1. To guarantee correct operation, before enabling
the peripheral (while I2CCR.PE=0), configure bit7
and bit6 of the I2COAR2 register according to the
internal clock INTCLK (for example 11xxxxxxb in
the range 14 - 30 MHz).
2. Bit7 of the I2CCR register must be cleared.
I
R240 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved
Must be cleared
Bit 5 = PE Peripheral Enable.
This bit is set and cleared by software.
0: Peripheral disabled (reset value)
1: Master/Slave capability
Notes:
– When I2CCR.PE=0, all the bits of the I2CCR
– When I2CCR.PE=1, the corresponding I/O pins
– To enable the I
– When PE=1, the FREQ[2:0] and EN10BIT bits in
Bit 4 = ENGC General Call address enable.
Setting this bit the peripheral works as a slave and
the value stored in the I2CADR register is recog-
nized as device address.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
0: The address stored in the I2CADR register is
2
2
C BUS INTERFACE (Cont’d)
C CONTROL REGISTER (I2CCR)
register and the I2CSR1-I2CSR2 registers ex-
cept the STOP bit are reset. All outputs will be re-
leased while I2CCR.PE=0
are selected by hardware as alternate functions
(open drain).
ister TWICE with I2CCR.PE=1 as the first write
only activates the interface (only I2CCR.PE is
set).
the I2COAR2 and I2CADR registers cannot be
written. The value of these bits can be changed
only when PE=0.
ignored (reset value)
7
0
0
PE
2
C interface, write the I2CCR reg-
ENGC
START ACK STOP ITE
0
1: The General Call address stored in the I2CADR
Note: The correct value (usually 00h) must be
written in the I2CADR register before enabling the
General Call feature.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0) or when the Start condition is
sent (with interrupt generation if ITE=1).
– In master mode:
– In slave mode:
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (I2CCR.PE=0).
0: No acknowledge returned (reset value)
1: Acknowledge returned after an address byte or
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also
cleared by hardware in master mode. It is not
cleared
(I2CCR.PE=0). In slave mode, this bit must be set
only when I2CSR1.BTF=1.
– In master mode:
– In slave mode:
0: No start generation
1: Repeated start generation
0: No start generation (reset value)
1: Start generation when the bus is free
0: No stop generation
1: Stop generation after the current byte transfer
or after the current Start condition is sent. The
STOP bit is cleared by hardware when the Stop
condition is sent.
0: No stop generation (reset value)
1: Release SCL and SDA lines after the current
byte transfer (I2CSR1.BTF=1). In this mode the
STOP bit has to be cleared by software.
register will be acknowledged
a data byte is received
when
the
I2C BUS INTERFACE
interface
is
disabled
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