ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 179

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
14.1
14.1.1
Table 119. Flash option bytes
1. Depends on device type as defined in
Default
HALT
7
1
WDG
Flash devices
Flash configuration
The option bytes allow the hardware configuration of the microcontroller to be selected.
They have no address in the memory map and can be accessed only in programming mode
(for example using a standard ST7 programming tool). The default content of the Flash is
fixed to FFh. To program directly the Flash devices using ICP, Flash devices are shipped to
customers with the internal RC clock source. In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option list).
Table 120. Option byte 0 bit description
OPT4:3
OPT2:1
OPT7
OPT6
OPT5
Bit
SW
6
1
Res
Static option byte 0
5
1
WDG HALT
WDG SW
VD[1:0]
Name
4
1
0
-
-
VD
Table 122: Package selection (OPT7) on page 181.
3
0
0
Watchdog reset on Halt
Hardware or software Watchdog
Reserved, must be kept at default value.
Voltage detection
Reserved, must be kept at default value
Reserved
2
1
This option bit determines if a reset is generated when entering Halt
mode while the Watchdog is active.
0: No reset generation when entering Halt mode
1: Reset generation when entering Halt mode
This option bit selects the Watchdog type.
0: Hardware (Watchdog always enabled)
1: Software (Watchdog to be enabled by software)
These option bits enable the voltage detection block (LVD and AVD)
with a selected threshold for the LVD and AVD.
00: Selected LVD = Highest threshold (V
01: Selected LVD = Medium threshold (V
10: Selected LVD = Lowest threshold (V
11: LVD and AVD off
Caution: If the medium or low thresholds are selected, the detection
may occur outside the specified operating voltage range. Below 3.8V,
device operation is not guaranteed. For details on the AVD and LVD
threshold levels refer to
1
1
0
1
Device configuration and ordering information
PKG1
note
See
7
1
Section 12.4.1 on page
6
1
Function
OSCTYPE
Static option byte 1
5
1
1
DD
DD
4
0
0
DD
~3V).
~4V).
~3.5V).
3
2
0
OSCRANGE
145.
2
1
1
1
0
1
179/193
0
1