ST72F324BJ6B6 STMicroelectronics, ST72F324BJ6B6 Datasheet - Page 163

• Manufacturer Part Number: ST72F324BJ6B6
• Description: MCU 8BIT 32KB FLASH/ROM 42-SDIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F324BJ6B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Controller Family/series: ST7
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• No. Of Pwm Channels: 3
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5589-5

ST72324Bxx
RESET pin protection when LVD is enabled
When the LVD is enabled, it is recommended to protect the RESET pin as shown in
Figure 78
1.
2.
3.
4.
5.
6.
Tips when using the LVD:
●
●
●
Figure 78. RESET pin protection when LVD is enabled
The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the V
Otherwise the reset will not be taken into account internally.
Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin (by an
external pull-up for example) is less than the absolute maximum value specified for
I
When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-
down capacitor is recommended to filter noise on the reset line.
In case a capacitive power supply is used, it is recommended to connect a 1M ohm
pull-down resistor to the RESET pin to discharge any residual voltage induced by this
capacitive power supply (this will add 5 µA to the power consumption of the MCU).
Check that all recommendations related to reset circuit have been applied (see section
above)
Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).
Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1 M Ohm
pull-down on the RESET pin.
The capacitors connected on the RESET pin and also the power supply are key to
avoiding any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: Replace 10 nF pull-down on the RESET pin with a 5 µF to
20 µF capacitor.
External
INJ(RESET)
reset
and follow these guidelines:
Recommended
in
Section 12.2.2 on page
0.01 µF
1 MΩ
Optional
(note 6)
V
DD
143.
IL
R
max. level specified in
ON
Filter
generator
Pulse
Electrical characteristics
Section
12.10.1.
Watchdog
LVD rese
ST72XXX
Internal
reset
t
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