ST7FLITE19F1M6 STMicroelectronics, ST7FLITE19F1M6 Datasheet - Page 112

• Manufacturer Part Number: ST7FLITE19F1M6
• Description: IC MCU 8BIT 4K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE19F1M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE1x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 1 x 12 bit / 2 x 8 bit
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit x 10 bit
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2133-5

ST7LITE1
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 84. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
112/131
OSC
1/t
Symbol
t
t
w(SCKH)
w(SCKL)
t
t
t
t
f
t
t
t
t
t
dis(SO)
t
t
t
r(SCK)
f(SCK)
su(SS)
t
SCK =
su(MI)
t
h(MO)
v(MO)
MISO
MOSI
h(SS)
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
c(SCK)
h(SI)
, and T
SS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
see note 2
t
a(SO)
t
Parameter
su(SS)
t
su(SI)
MSB IN
t
t
w(SCKH)
w(SCKL)
MSB OUT
t
t
h(SI)
c(SCK)
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (before capture edge)
t
DD
v(SO)
DD
,
BIT6 OUT
and 0.7xV
Conditions
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
DD
BIT1 IN
f
f
.
CPU
CPU
t
h(SO)
=8MHz
=8MHz
t
t
r(SCK)
f(SCK)
f
CPU
0.0625
see I/O port pin description
0.25
0.25
Min
120
120
100
100
100
100
100
90
/128 =
0
0
0
LSB IN
LSB OUT
t
h(SS)
f
CPU
f
CPU
Max
120
240
120
2
4
/4 =
/2
t
dis(SO)
Unit
t
MHz
CPU
ns
note 2
see