LPC3220FET296/01,5 NXP Semiconductors, LPC3220FET296/01,5 Datasheet - Page 4

• Manufacturer Part Number: LPC3220FET296/01,5
• Description: IC ARM9 MCU 128K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3220FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4965; 935290763551

NXP Semiconductors
3. Functional problems detail
ES_LPC3220
Errata sheet
Fig 1.
Scope shot 1 - expected read timing
3.1 DMA.1: Single burst DMA memory-to-memory transfers have
additional memory cycles when the DMA source memory is on the
EMC bus
Introduction:
The DMA controller is an AHB master that can transfer blocks of data between
peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and
memory-to-memory. In addition to transferring data between memories, a DMA
memory-to-memory flow can be used to transfer blocks of data to / from an FPGA or
external peripheral chip connected to an EMC static memory chip select. When a memory,
FPGA or external peripheral chip does not support burst transfers (i.e. multiple reads for
each active chip select or read strobe) the burst size for that memory-to-memory flow
must be set for one transfer per burst.
Problem:
When using memory-to-memory DMA with the EMC static chip select (EMC_CS[x]_N) as
the DMA source and the DMA channel source burst size is set for a single transfer
(DMACCxControl:SBSIZE = 0), each DMA source read should be a single bus-wide
access. The access should be similar to reading the EMC_CS[x]_N static memory with an
ARM LDR instruction, as shown in
controlled by the EMCSTATICx registers. In all example scope shots the
EMCSTATICWAITx registers are set to the maximum value.
However, the actual EMC timing for the source DMA read is a double wide chip select with
a burst of two reads (notice how the address increments near the halfway point of nCS0
active), see
destination write (also to nCS0 in
value read during the read burst. When the DMA source address is set to auto-increment,
the last DMA read transfer will address the last address of the source buffer and the last
source buffer address +1. This behavior only happens during the read part of the DMA
transfer. Memory-to-memory DMA destination writes to the EMC static chip select work as
expected.
Figure
All information provided in this document is subject to legal disclaimers.
2. The second data read during the burst is discarded, as the DMA
Rev. 8 — 1 February 2011
Figure
Figure
2) following each read, always writes the first
1. Note the EMC signal timing for the read is
ES_LPC3220
Errata sheet LPC3220
© NXP B.V. 2011. All rights reserved.
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