LPC3220FET296/01,5 NXP Semiconductors, LPC3220FET296/01,5 Datasheet - Page 16

• Manufacturer Part Number: LPC3220FET296/01,5
• Description: IC ARM9 MCU 128K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3220FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4965; 935290763551

NXP Semiconductors
6. Contents
1
2
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
4.1
5
5.1
Product identification . . . . . . . . . . . . . . . . . . . . 3
Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional problems detail . . . . . . . . . . . . . . . . 4
AC/DC deviations detail . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
DMA.1: Single burst DMA memory-to-memory
transfers have additional memory cycles when the
DMA source memory is on the EMC bus . . . . . 4
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6
NOR.1: When booting from NOR flash, SDRAM
devices will not release the data bus, preventing
the LPC3220 from booting correctly . . . . . . . . . 6
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DDR.2: DDR EMC_D[15:0] to EMC_DQS[1:0]
data output set-up time, t
DDR provides limited timing margin . . . . . . . . . 8
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DDR.1: DDR interface has >1.2 ns clock skew 10
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .10
RTC.1: An RTC match doesn’t drive the ONSW
pin active (HIGH) . . . . . . . . . . . . . . . . . . . . . . 11
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .11
INT.1: GPI_08 does not generate an interrupt
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .11
MCPWM.1: Input pins (MCI0-2) on the Motor
Control PWM peripheral are not functional. . . 12
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .12
ESD.1: Weak ESD protection on Reset_N pad 12
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
su(Q)
, for MCU write to
5.2
5.3
6
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ES_LPC3220
Errata sheet LPC3220
Document identifier: ES_LPC3220
Date of release: 1 February 2011
All rights reserved.