LPC3250FET296,551 NXP Semiconductors, LPC3250FET296,551 Datasheet - Page 32
![IC ARM9 MCU 256K 296-TFBGA](/photos/12/13/121385/296-tfbga_sot1048-1_sml.jpg)
LPC3250FET296,551
Manufacturer Part Number
LPC3250FET296,551
Description
IC ARM9 MCU 256K 296-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC32x0r
Datasheet
1.OM11079.pdf
(77 pages)
Specifications of LPC3250FET296,551
Core Processor
ARM9
Core Size
16/32-Bit
Speed
266MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, Motor Control PWM, PWM, WDT
Number Of I /o
51
Program Memory Type
ROMless
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 3.6 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
296-TFBGA
Processor Series
LPC32
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
256 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
51
Number Of Timers
6
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-57TS-LPC3250, DK-57VTS-LPC3250, SOMDIMM-LPC3250
Development Tools By Supplier
OM11016, OM11021, OM11045
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
OM11021 - EVAL LPC-STICK WITH LPC3250OM11016 - KIT DEVELOPMENT LPC3250568-4743 - KIT LCD TOUCH 5.7" FOR LPC3250568-4742 - MODULE DIMM LPC2478 ARM7622-1030 - KIT LCD TOUCH 5.7" FOR LPC3250
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4533
935287084551
935287084551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC3250FET296,551
Manufacturer:
BONENS
Quantity:
98
Company:
Part Number:
LPC3250FET296,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC3220_30_40_50_1
Product data sheet
7.6.4.1 Features
7.6.4 LCD controller
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 × 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
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Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for
dual-role devices under software control. HNP is partially implemented in hardware.
Provides programmable timers required for HNP and SRP.
Supports slave mode operation through AHB slave interface.
Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG
specification compliant ATX.
AHB bus master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
Supports single and dual-panel color STN displays.
Supports Thin Film Transistor (TFT) color displays.
Programmable display resolution including, but not limited to: 320 × 200, 320 × 240,
640 × 200, 640 × 240, 640 × 480, 800 × 600, and 1024 × 768.
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32 k color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized, for color STN and TFT.
24 bpp true-color non-palettized, for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128 × 32 bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock may be generated from the peripheral clock or from a clock input pin.
All information provided in this document is subject to legal disclaimers.
Rev. 01.03 — 16 March 2010
LPC3220/30/40/50
16/32-bit ARM microcontrollers
© NXP B.V. 2010. All rights reserved.
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