AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 682

• Manufacturer Part Number: AT91SAM9XE512-QU
• Description: MCU ARM9 512K FLASH 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Controller Family/series: AT91SAM9xxxxx
• No. Of I/o's: 96
• Ram Memory Size: 32KB
• Cpu Speed: 180MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Package: 208PQFP
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

38.5.5
Register Name:
Address:
Access Type:
This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start
location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original
values after either 1024 buffers or when the wrap bit of the entry is set.
Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are
used. Software should not use this register for determining where to remove received frames from the queue as it con-
stantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue
checking the used bits.
Receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is
always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification.
• ADDR:
Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.
682
31
23
15
7
AT91SAM9XE128/256/512 Preliminary
Receive buffer queue pointer address
Receive Buffer Queue Pointer Register
30
22
14
EMAC_RBQP
0xFFFC4018
Read-write
6
29
21
13
5
ADDR
28
20
12
4
ADDR
ADDR
ADDR
27
19
11
3
26
18
10
2
25
17
9
1
–
6254C–ATARM–22-Jan-10
24
16
8
0
–