AT91SAM9XE512-QU Atmel, AT91SAM9XE512-QU Datasheet - Page 211

• Manufacturer Part Number: AT91SAM9XE512-QU
• Description: MCU ARM9 512K FLASH 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE512-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Controller Family/series: AT91SAM9xxxxx
• No. Of I/o's: 96
• Ram Memory Size: 32KB
• Cpu Speed: 180MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Package: 208PQFP
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.9
23.9.1
23.9.2
6254C–ATARM–22-Jan-10
Automatic Wait States
Chip Select Wait States
Early Read Wait State
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the de-activation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to
NWR3, NCS[0..7], NRD lines are all set to 1.
Figure 23-16
Select 2.
Figure 23-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
NBS0, NBS1,
NBS2, NBS3,
A0,A1
• if the write controlling signal has no hold time and the read controlling signal has no setup
time
A[25:2]
D[31:0]
NCS0
NCS2
NWE
MCK
NRD
(Figure
illustrates a chip select wait state between access on Chip Select 0 and Chip
NCS2
23-17).
AT91SAM9XE128/256/512 Preliminary
NRD_CYCLE
Read to Write
Wait State
Chip Select
Wait State
NWE_CYCLE
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