PIC17C44-25/L Microchip Technology, PIC17C44-25/L Datasheet - Page 21

• Manufacturer Part Number: PIC17C44-25/L
• Description: IC MCU OTP 8KX16 PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C44-25/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.0
The PIC17C4X devices have 11 sources of interrupt:
• External interrupt from the RA0/INT pin
• Change on RB7:RB0 pins
• TMR0 Overflow
• TMR1 Overflow
• TMR2 Overflow
• TMR3 Overflow
• USART Transmit buffer empty
• USART Receive buffer full
• Capture1
• Capture2
• T0CKI edge occurred
There are four registers used in the control and status
of interrupts. These are:
• CPUSTA
• INTSTA
• PIE
• PIR
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Memory Orga-
nization section.
FIGURE 5-1:
1996 Microchip Technology Inc.
TMR1IF
TMR1IE
INTERRUPTS
TMR2IF
TMR2IE
RBIF
RBIE
INTERRUPT LOGIC
TMR3IF
TMR3IE
RCIF
RCIE
CA2IF
CA2IE
TXIF
TXIE
CA1IF
CA1IE
This document was created with FrameMaker 4 0 4
GLINTD
T0CKIF
T0CKIE
INTF
INTE
PEIF
PEIE
T0IF
T0IE
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts which
have the same vector address). These sources are:
• External interrupt from the RA0/INT pin
• TMR0 Overflow
• T0CKI edge occurred
• Any peripheral interrupt
When program execution vectors to one of these inter-
rupt vector addresses (except for the peripheral inter-
rupt address), the interrupt flag bit is automatically
cleared. Vectoring to the peripheral interrupt vector
address does not automatically clear the source of the
interrupt. In the peripheral interrupt service routine, the
source(s) of the interrupt can be determined by testing
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
All of the individual interrupt flag bits will be set regard-
less of the status of their corresponding mask bit or the
GLINTD bit.
For external interrupt events, there will be an interrupt
latency. For two cycle instructions, the latency could be
one instruction cycle longer.
The “return from interrupt” instruction, RETFIE , can be
used to mark the end of the interrupt service routine.
When this instruction is executed, the stack is
“POPed”, and the GLINTD bit is cleared (to re-enable
interrupts).
PIC17C4X
Wake-up (If in SLEEP mode)
or terminate long write
DS30412C-page 21
Interrupt to CPU