PIC17C44-25/L Microchip Technology, PIC17C44-25/L Datasheet - Page 124

• Manufacturer Part Number: PIC17C44-25/L
• Description: IC MCU OTP 8KX16 PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C44-25/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC17C4X
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
DS30412C-page 124
Before Instruction
After Instruction
Forced NOP
Decode
REG
REG
If REG
If REG
Q1
Q1
PC =
PC =
=
=
=
=
register 'f'
Increment f, skip if not 0
[ label ]
0
d
(f) + 1
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making
it a two-cycle instruction.
1
1(2)
HERE
ZERO
NZERO
None
Read
NOP
0010
Q2
Q2
REG
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
f
[0,1]
255
INFSNZ f,d
(dest), skip if not 0
INFSNZ
010d
Execute
Execute
Q3
Q3
REG, 1
ffff
destination
Write to
NOP
Q4
Q4
ffff
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
WREG
Q1
=
=
Inclusive OR Literal with WREG
[ label ]
0
(WREG) .OR. (k)
Z
The contents of WREG are OR’ed with
the eight bit literal 'k'. The result is
placed in WREG.
1
1
IORLW
literal 'k'
Read
1011
Q2
0x9A
0xBF
k
1996 Microchip Technology Inc.
255
IORLW k
0011
0x35
Execute
Q3
kkkk
(WREG)
Write to
WREG
Q4
kkkk