PIC17C44-25/L Microchip Technology, PIC17C44-25/L Datasheet - Page 119

• Manufacturer Part Number: PIC17C44-25/L
• Description: IC MCU OTP 8KX16 PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C44-25/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
1996 Microchip Technology Inc.
Before Instruction
After Instruction
Forced NOP
Decode
PC Address
WREG
REG
If REG
If REG
Q1
Q1
PC
PC
register 'f'
Compare f with WREG,
skip if f = WREG
[ label ] CPFSEQ
0
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If 'f' = WREG then the fetched instruc-
tion is discarded and an NOP is exe-
cuted instead making this a two-cycle
instruction.
1
1 (2)
HERE
NEQUAL
EQUAL
None
Read
NOP
0011
Q2
Q2
=
=
=
=
=
=
f
255
HERE
?
?
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
CPFSEQ REG
:
:
0001
Execute
Execute
Q3
Q3
ffff
f
NOP
NOP
Q4
Q4
ffff
CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
Before Instruction
After Instruction
Forced NOP
Decode
PC
WREG
If REG
If REG
Q1
Q1
PC
PC
register 'f'
Compare f with WREG,
skip if f > WREG
[ label ] CPFSGT
0
(f)
skip if (f) > (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location 'f' to the contents of the WREG
by performing an unsigned subtraction.
If the contents of 'f' > the contents of
WREG then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruc-
tion.
1
1 (2)
HERE
NGREATER
GREATER
Read
NOP
0011
Q2
Q2
=
=
>
=
f
=
WREG),
255
Address (HERE)
?
WREG;
Address (GREATER)
WREG;
Address (NGREATER)
PIC17C4X
0010
CPFSGT REG
:
:
Execute
Execute
Q3
Q3
DS30412C-page 119
ffff
f
NOP
NOP
Q4
Q4
ffff