ATMEGA3290PV-10AU Atmel, ATMEGA3290PV-10AU Datasheet - Page 59

• Manufacturer Part Number: ATMEGA3290PV-10AU
• Description: IC MCU 32K 4X40 LCD CTRL 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3290PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA3290PV-8AU; ATMEGA3290PV-8AU

12.2
12.3
12.3.1
8021G–AVR–03/11
Pin Change Interrupt Timing
Register Description
EICRA – External Interrupt Control Register A
An example of timing of a pin change interrupt is shown in
Figure 12-1. Pin Change Interrupt
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Bit
(0x69)
Read/Write
Initial Value
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
R
7
–
0
LE
Table 12-1 on page
pin_lat
R
6
–
0
D
Q
pin_sync
R
5
–
0
PCINT(0) in PCMSK(x)
R
4
–
0
60. The value on the INT0 pin is sampled before
pcint_in_(0)
0
x
R
clk
3
–
0
ATmega329P/3290P
Figure
R
2
–
0
pcint_syn
12-1.
ISC01
R/W
1
0
pcint_setflag
ISC00
R/W
0
0
PCIF
EICRA
59