ATMEGA3290PV-10AU Atmel, ATMEGA3290PV-10AU Datasheet - Page 292

• Manufacturer Part Number: ATMEGA3290PV-10AU
• Description: IC MCU 32K 4X40 LCD CTRL 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3290PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA3290PV-8AU; ATMEGA3290PV-8AU

26.8.13
26.8.13.1
In
Table 26-6.
Note:
8021G–AVR–03/11
BOOTSZ1
Table 26-6
1
1
0
0
1. The different BOOTSZ Fuse configurations are shown in
Boot Loader Parameters
ATmega329P/3290P
through
BOOTSZ0
Boot Size Configuration (ATmega329P/3290P)
1
0
1
0
Table
26-8, the parameters used in the description of the Self-Programming are given.
1024 words
2048 words
Return:
Do_spm:
Wait_spm:
Wait_ee:
Boot Size
256 words
512 words
brne Rdloop
; return to RWW section
; verify that RWW section is safe to read
in
sbrs temp1, RWWSB
ret
; re-enable the RWW section
ldi
call Do_spm
rjmp Return
; check for previous SPM complete
in
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
cli
; check that no EEPROM write access is present
sbic EECR, EEWE
rjmp Wait_ee
; SPM timed sequence
out
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
temp1, SPMCSR
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
temp1, SPMCSR
temp2, SREG
SPMCSR, spmcrval
SREG, temp2
Pages
16
32
4
8
Application
Flash Section
0x0000-0x3EFF
0x0000-0x3DFF
0x0000-0x3BFF
0x0000-0x37FF
; If RWWSB is set, the RWW section is not ready yet
(1)
Figure 26-2
Boot Loader
Flash Section
0x3F00-0x3FFF
0x3E00-0x3FFF
0x3C00-0x3FFF
0x3800-0x3FFF
ATmega329P/3290P
End
Application
Section
0x3EFF
0x3DFF
0x3BFF
0x37FF
Boot Reset
Address
(Start
Boot Loader
Section)
0x3F00
0x3E00
0x3C00
0x3800
292