ATMEGA3290PV-10AU Atmel, ATMEGA3290PV-10AU Datasheet - Page 217

• Manufacturer Part Number: ATMEGA3290PV-10AU
• Description: IC MCU 32K 4X40 LCD CTRL 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3290PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA3290PV-8AU; ATMEGA3290PV-8AU

8021G–AVR–03/11
with Auto triggering from a source other than the ADC Conversion Complete, each conversion
will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after
every conversion.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see
Figure 22-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 22-5. ADC Timing Diagram, Single Conversion
Figure 22-6. ADC Timing Diagram, Auto Triggered Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Prescaler
Reset
1
1
2
MUX and REFS
Update
MUX and REFS
Update
1
2
MUX and REFS
Update
12
2
3
13
Sample & Hold
3
4
Sample &
Hold
14
4
5
15
5
6
Sample & Hold
16
6
First Conversion
17
7
One Conversion
18
7
8
One Conversion
19
8
9
20
9
10
Conversion
ATmega329P/3290P
Complete
21
10
Conversion
11
Complete
22
Conversion
Complete
11
23
12
24
12
13
25
13
Sign and MSB of Result
Sign and MSB of Result
Table
LSB of Result
Next Conversion
Sign and MSB of Result
1
Next
Conversion
1
LSB of Result
LSB of Result
2
2
22-1.
MUX and REFS
Update
Next Conversion
MUX and REFS
Update
1
Prescaler
Reset
3
3
2
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