AT89C5131A-S3SUM Atmel, AT89C5131A-S3SUM Datasheet - Page 79

• Manufacturer Part Number: AT89C5131A-S3SUM
• Description: IC 8051 MCU FLASH 32K USB 52PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Package: 52PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16. Interrupt System
16.1
Figure 16-1. Interrupt Control System
4337K–USB–04/08
Overview
USBINT
UEPINT
EXF2
KBD IT
TWI IT
SPI IT
INT0
INT1
TF0
PCA IT
TF1
TF2
RI
TI
TCON.0
TCON.2
IT0
IT1
Individual Enable
The AT89C5130A/31A-M has a total of 11 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard
interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1.
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register
which must be cleared to disable all interrupts at once.
IE0
IE1
IPH, IPL
(Table
Global Disable
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
16-2). This register also contains a global disable bit,
AT89C5130A/31A-M
High priority
interrupt
Interrupt
Polling
Sequence, Decreasing From
High-to-Low Priority
Low Priority
Interrupt
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