AT89C5131A-S3SUM Atmel, AT89C5131A-S3SUM Datasheet - Page 140

• Manufacturer Part Number: AT89C5131A-S3SUM
• Description: IC 8051 MCU FLASH 32K USB 52PLCC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131A-S3SUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: 2-Wire, EUART, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Package: 52PLCC
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

140
AT89C5130A/31A-M
Table 21-4.
Reset Value = 00h
Bit Number
7-6
7
5
4
3
2
1
0
-
Mnemonic
WUPCPU
EORINT
USBINT Register
USBINT (S:BDh)
USB Global Interrupt Register
SOFINT
SPINT
Bit
6
-
-
-
-
Description
Reserved
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt
This bit is set by hardware when the USB controller is in SUSPEND state and is re-
activated by a non-idle signal FROM USB line (not by an upstream resume). This
triggers a USB interrupt when EWUPCPU is set in Figure 21-5 on page 141.
When receiving this interrupt, user has to enable all USB clock inputs.
This bit will be cleared by software (USB clocks must be enabled before).
End Of Reset Interrupt
This bit is set by hardware when a End Of Reset has been detected by the USB
controller. This triggers a USB interrupt when EEORINT is set (see
141).
This bit will be cleared by software.
Start of Frame Interrupt
This bit is set by hardware when an USB Start of Frame PID (SOF) has been detected.
This triggers a USB interrupt when ESOFINT is set (see
This bit will be cleared by software.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is always 0. Do not set this bit.
Suspend Interrupt
This bit is set by hardware when a USB Suspend (Idle bus for three frame periods: a J
state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in see
Table 21-5 on page
This bit will be cleared by software BEFORE any other USB operation to re-activate the
macro.
WUPCPU
5
EORINT
141.
4
SOFINT
3
2
-
Table 21-5 on page
1
-
Table 21-5 on page
4337K–USB–04/08
141).
SPINT
0