ATMEGA329V-8AU Atmel, ATMEGA329V-8AU Datasheet - Page 69

• Manufacturer Part Number: ATMEGA329V-8AU
• Description: IC AVR MCU 32K 8MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 54
• Interface: SPI/UART/USART/USI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 32K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.7-5.5 V
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ATmega329/3210/649/6410
PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external inter-
rupt source.
• OC1B/PCINT14, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output
(DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM
mode timer function.
PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external inter-
rupt source.
• OC1A/PCINT13, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output
for the Timer/Counter1 Output Compare A. The pin has to be configured as an output
(DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM
mode timer function.
PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external inter-
rupt source.
• OC0A/PCINT12, Bit 4
OC0A, Output Compare Match A output: The PB4 pin can serve as an external output
for the Timer/Counter0 Output Compare A. The pin has to be configured as an output
(DDB4 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM
mode timer function.
PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external inter-
rupt source.
• MISO/PCINT11 – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a
Master, this pin is configured as an input regardless of the setting of DDB3. When the
SPI is enabled as a Slave, the data direction of this pin is controlled by DDB3. When the
pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.
PCINT11, Pin Change Interrupt Source 11: The PB3 pin can serve as an external inter-
rupt source.
• MOSI/PCINT10 – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI
is enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin
is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.
PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external inter-
rupt source.
• SCK/PCINT9 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI
is enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin
is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.
PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt
source.
69
2552H–AVR–11/06