ATMEGA329V-8AU Atmel, ATMEGA329V-8AU Datasheet
ATMEGA329V-8AU
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ATMEGA329V-8AU Summary of contents
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... I/O and Packages – 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP • Speed Grade: – ATmega329V/ATmega3290V/ATmega649V/ATmega6490V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega329/3290/649/6490 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial ® ...
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Features (Continued) • Ultra-Low Power Consumption – Active Mode: 1 MHz, 1.8V: 350 µA 32 kHz, 1.8V: 20 µA (including Oscillator) 32 kHz, 1.8V: 40 µA (including Oscillator and LCD) – Power-down Mode: 100 nA at 1.8V Pin Configurations ATmega329/3290/649/6490 ...
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Disclaimer 2552H–AVR–11/06 Figure 2. Pinout ATmega329/649 LCDCAP 1 (RXD/PCINT0) PE0 2 INDEX CORNER (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 ...
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Overview The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architec- ture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega329/3290/649/6490 AVR is supported with a full suite of program and sys- tem development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits ...
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Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490 Pin Descriptions V CC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) ATmega329/3290/649/6490 6 The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes, pin count and ...
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Port E (PE7..PE0) Port F (PF7..PF0) Port G (PG5..PG0) Port H (PH7..PH0) Port J (PJ6..PJ0) RESET XTAL1 2552H–AVR–11/ ...
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... A comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...
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AVR CPU Core Introduction Architectural Overview 2552H–AVR–11/06 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...
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ALU – Arithmetic Logic Unit ATmega329/3290/649/6490 10 the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register ...
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AVR Status Register SREG – AVR Status Register 2552H–AVR–11/06 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note ...
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General Purpose Register File ATmega329/3290/649/6490 12 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit ...
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The X-register, Y-register, and Z-register Stack Pointer 2552H–AVR–11/06 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, ...
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Instruction Execution Timing Reset and Interrupt Handling ATmega329/3290/649/6490 14 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. ...
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Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 268. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are ...
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Interrupt Response Time ATmega329/3290/649/6490 16 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter ...
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AVR ATmega329/3290/649/6490 Memories In-System Reprogrammable Flash Program Memory 2552H–AVR–11/06 This section describes the different memories in the ATmega329/3290/649/6490. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega329/3290/649/6490 features an ...
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SRAM Data Memory Data Memory Access Times ATmega329/3290/649/6490 18 Figure 10 shows how the ATmega329/3290/649/6490 SRAM Memory is organized. The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the ...
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EEPROM Data Memory EEPROM Read/Write Access 2552H–AVR–11/06 Figure 11. On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction The ATmega329/3290/649/6490 contains 1/2K bytes of data EEPROM memory organized as ...
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EEARH and EEARL – The EEPROM Address Register EEDR – The EEPROM Data Register EECR – The EEPROM Control Register ATmega329/3290/649/6490 20 Bit 0x22 (0x42) – – – 0x21 (0x41) EEAR7 EEAR6 EEAR5 Read/Write ...
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Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the ...
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ATmega329/3290/649/6490 22 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during execution of ...
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EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption 2552H–AVR–11/06 Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ...
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I/O Memory General Purpose I/O Registers The ATmega329/3290/649/6490 contains three General Purpose I/O Registers. These GPIOR2 – General Purpose I/O Register 2 GPIOR1 – General Purpose I/O Register 1 GPIOR0 – General Purpose I/O Register 0 ATmega329/3290/649/6490 24 level of ...
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System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O Flash Clock – clk FLASH Asynchronous Timer Clock – clk ASY 2552H–AVR–11/06 Figure 12 presents the principal clock systems in ...
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ADC Clock – clk ADC Clock Sources Default Clock Source Crystal Oscillator ATmega329/3290/649/6490 26 The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. ...
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Figure 13. Crystal Oscillator Connections C2 C1 The Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5. Table 5. ...
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Low-frequency Crystal Oscillator Calibrated Internal RC Oscillator ATmega329/3290/649/6490 28 Notes: 1. These options should only be used when not operating close to the maximum fre- quency of the device, and only if frequency stability at start-up is not important for ...
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OSCCAL – Oscillator Calibration Register 2552H–AVR–11/06 Table 9. Internal Calibrated RC Oscillator Operating Modes (2) Frequency Range 7.3 - 8.1 Notes: 1. The device is shipped with this option selected. 2. The frequency ranges are preliminary values. Actual values are ...
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External Clock ATmega329/3290/649/6490 30 To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. Figure ...
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Clock Output Buffer Timer/Counter Oscillator System Clock Prescaler CLKPR – Clock Prescale Register 2552H–AVR–11/06 When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is suitable when the chip clock is used to drive ...
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Switching Time ATmega329/3290/649/6490 32 The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro- grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a ...
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Power Management and Sleep Modes Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Sleep Mode Idle X ADC Noise Reduction Power- down Power- save (1) Standby Notes: 1. Only recommended with external ...
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Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode ATmega329/3290/649/6490 34 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog ...
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Standby Mode Power Reduction Register 2552H–AVR–11/06 The LCD controller and Timer/Counter2 can be clocked both synchronously and asyn- chronously in Power-save mode. The clock source for the two modules can be selected independent of each other. If neither the LCD ...
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Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins ATmega329/3290/649/6490 36 There are several possibilities to consider when trying to minimize the power consump- tion in an AVR controlled system. In ...
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JTAG Interface and On-chip Debug System 2552H–AVR–11/06 ters (DIDR1 and DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” on page 202 and “DIDR0 – Digital Input Disable Register 0” on page 219 for details. If the On-chip debug ...
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Register Description SMCR – Sleep Mode Control Register PRR – Power Reduction Register ATmega329/3290/649/6490 38 The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) – – – Read/Write Initial ...
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Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper operation. • Bit 1 - PRUSART: ...
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System Control and Reset Resetting the AVR Reset Sources ATmega329/3290/649/6490 40 During reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must ...
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Power-on Reset 2552H–AVR–11/06 Figure 15. Reset Logic Power-on Reset Brown-out BODLEVEL [1..0] Reset Circuit Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Generator CKSEL[3:0] SUT[1:0] Table 16. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on ...
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External Reset Brown-out Detection ATmega329/3290/649/6490 42 Figure 16. MCU Start-up, RESET Tied POT RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 17. MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL ...
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Watchdog Reset 2552H–AVR–11/06 teresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted BOT+ Table 17. BODLEVEL Fuse Coding BODLEVEL 2:0 Fuses Note may ...
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MCUSR – MCU Status Register ATmega329/3290/649/6490 44 Figure 20. Watchdog Reset During Operation CC The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) – – – Read/Write R R ...
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Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer 2552H–AVR–11/06 ATmega329/3290/649/6490 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ...
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WDTCR – Watchdog Timer Control Register ATmega329/3290/649/6490 46 Figure 21. Watchdog Timer WATCHDOG OSCILLATOR Bit (0x60) – – – Read/Write Initial Value • Bits 7:5 – Res: Reserved Bits These bits ...
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Table 21. Watchdog Timer Prescale Select Number of WDT WDP2 WDP1 WDP0 Oscillator Cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles ...
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Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 1 Safety Level 2 ATmega329/3290/649/6490 48 The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. In this mode, ...
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Interrupts Interrupt Vectors in ATmega329/3290/649/6490 2552H–AVR–11/06 This section describes the specifics of the interrupt handling as performed in ATmega329/3290/649/6490. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 14. Table 22. Reset ...
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ATmega329/339/649/659 50 Table 23 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset ...
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Moving Interrupts Between Application and Boot Space MCUCR – MCU Control Register ATmega329/339/649/659 52 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start 0x382F/0x782F out SPH,r16 0x3830/0x7830 ldi r16,low(RAMEND) 0x3831/0x7831 out SPL,r16 0x3832/0x7832 sei 0x3833/0x7833 <instr> xxx The MCU Control Register controls the placement of ...
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Assembly Code Example Move_interrupts: ;Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret C ...
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External Interrupts Pin Change Interrupt Timing ATmega329/3290/649/6490 54 The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30..0 pins are configured ...
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EICRA – External Interrupt Control Register A 2552H–AVR–11/06 The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) – – – Read/Write Initial Value • Bit ...
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External Interrupt Mask Register – EIMSK ATmega329/3290/649/6490 56 Bit PCIE3 PCIE2 PCIE1 Read/Write R/W R/W R/W Initial Value • Bit 7 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set ...
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EIFR – External Interrupt Flag Register PCMSK3 – Pin Change Mask (1) Register 3 2552H–AVR–11/06 Bit 0x1C (0x3C) PCIF3 PCIF2 PCIF1 Read/Write R/W R/W R/W Initial Value • Bit 7 – PCIF3: Pin Change ...
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PCMSK2 – Pin Change Mask (1) Register 2 PCMSK1 – Pin Change Mask Register 1 PCMSK0 – Pin Change Mask Register 0 ATmega329/3290/649/6490 58 Bit (0x6D) PCINT23 PCINT22 PCINT21 Read/Write R/W R/W R/W Initial ...
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I/O-Ports Introduction 2552H–AVR–11/06 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with ...
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Ports as General Digital I/O Configuring the Pin ATmega329/3210/649/6410 60 in “Alternate Port Functions” on page 65. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of ...
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Toggling the Pin Switching Between Input and Output Reading the Pin Value 2552H–AVR–11/06 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic ...
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ATmega329/3210/649/6410 62 Figure 25. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK XXX INSTRUCTIONS SYNC LATCH PINxn r17 XXX in r17, PINx 0x00 t pd, max t pd, min 2552H–AVR–11/06 0xFF ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of ...
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Digital Input Enable and Sleep Modes Unconnected Pins ATmega329/3210/649/6410 64 (1) Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17 ; Insert nop for ...
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Alternate Port Functions 2552H–AVR–11/06 described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of ...
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ATmega329/3210/649/6410 66 Table 26 summarizes the function of the overriding signals. The pin and port indexes from Figure 27 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. ...
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MCUCR – MCU Control Register Alternate Functions of Port A 2552H–AVR–11/06 Bit 7 6 0x35 (0x55) JTD – Read/Write R/W R Initial Value 0 0 • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the ...
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Alternate Functions of Port B ATmega329/3210/649/6410 68 Table 29. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/COM3 PA2/COM2 PUOE LCDEN • LCDEN • (LCDMUX) (LCDMUX) PUOV 0 0 DDOE LCDEN • LCDEN • (LCDMUX) (LCDMUX) DDOV 0 0 ...
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PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external inter- rupt source. • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 ...
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ATmega329/3210/649/6410 70 • SS/PCINT8 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0 Slave, the SPI ...
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Alternate Functions of Port C 2552H–AVR–11/06 Table 32. Overriding Signals for Alternate Functions in PB3:PB0 Signal PB3/MISO/ Name PCINT11 PUOE SPE • MSTR PUOV PORTB3 • PUD DDOE SPE • MSTR DDOV 0 PVOE SPE • MSTR PVOV SPI SLAVE ...
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ATmega329/3210/649/6410 72 Table 34. Overriding Signals for Alternate Functions in PC7:PC4 Signal Name PC7/SEG5 PC6/SEG6 PUOE LCDEN LCDEN PUOV 0 0 DDOE LCDEN LCDEN DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE LCDEN LCDEN DIEOV ...
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Alternate Functions of Port D 2552H–AVR–11/06 The Port D pins with alternate functions are shown in Table 36. Table 36. Port D Pins Alternate Functions (SEG refers to 100-pin/64-pin pinout) Port Pin Alternate Function PD7 SEG (LCD front plane 19/15) ...
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ATmega329/3210/649/6410 74 Table 37. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PD7/SEG(19/15) PD6/SEG(20/16) PUOE LCDEN • LCDEN • (LCDPM) (LCDPM) PUOV 0 0 DDOE LCDEN • LCDEN • (LCDPM) (LCDPM) DDOV 0 0 PVOE 0 0 PVOV 0 0 ...
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Alternate Functions of Port E 2552H–AVR–11/06 The Port E pins with alternate functions are shown in Table 39. Table 39. Port E Pins Alternate Functions Port Pin Alternate Function PCINT7 (Pin Change Interrupt7) PE7 CLKO (Divided System Clock) PE6 DO/PCINT6 ...
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ATmega329/3210/649/6410 76 • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 operates ...
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Alternate Functions of Port F 2552H–AVR–11/06 Table 41. Overriding Signals for Alternate Functions in PE3:PE0 Signal PE3/AIN1/ Name PCINT3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE – DIEOE (PCINT3 • PCIE0) + (1) AIN1D ...
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ATmega329/3210/649/6410 78 • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis- ter. When the JTAG interface is enabled, this pin ...
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Alternate Functions of Port G 2552H–AVR–11/06 Table 44. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PF3/ADC3 PUOE 0 PUOV 0 DDOE 0 DDOV 0 PVOE 0 PVOV 0 PTOE – DIEOE 0 DIEOV 0 DI – AIO ADC3 ...
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ATmega329/3210/649/6410 80 • SEG – Port G, Bit 1 SEG, Segment driver 17/13. • SEG – Port G, Bit 0 SEG, LCD front plane 18/14. Table 45 and Table 46 relates the alternate functions of Port G to the overriding ...
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Alternate Functions of Port H 2552H–AVR–11/06 Port H is only present in ATmega3290/6490. The alternate pin configuration is as follows: Table 48. Port H Pins Alternate Functions Port Pin Alternate Function PH7 PCINT23/SEG (Pin Change Interrupt23 or LCD Front Plane ...
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ATmega329/3210/649/6410 82 • PCINT17/SEG – Port H, Bit 1 PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external inter- rupt source. SEG, LCD front plane 9. • PCINT16/SEG – Port H, Bit 0 PCINT16, Pin ...
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Alternate Functions of Port J 2552H–AVR–11/06 Table 50. Overriding Signals for Alternate Functions in PH3:0 Signal PH3/PCINT19/ Name SEG7 PUOE LCDEN PUOV 0 DDOE LCDEN DDOV 0 PVOE 0 PVOV 0 PTOE – DIEOE PCINT19 • PCIE0 •LCDEN • LCDPM ...
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ATmega329/3210/649/6410 84 • PCINT28/SEG – Port J, Bit 4 PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external inter- rupt source. SEG, LCD front plane 29. • PCINT27/SEG – Port J, Bit 3 PCINT27, Pin ...
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Table 53. Overriding Signals for Alternate Functions in PH3:0 Signal PJ3/PCINT27/ Name SEG30 PUOE LCDEN PUOV 0 DDOE LCDEN DDOV 0 PVOE 0 PVOV 0 PTOE – DIEOE PCINT27 • PCIE0 •LCDEN • LCDPM DIEOV DI AIO LCDSEG ATmega329/3210/649/6410 ...
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Register Description for I/O-Ports PORTA – Port A Data Register DDRA – Port A Data Direction Register PINA – Port A Input Pins Address PORTB – Port B Data Register DDRB – Port B Data Direction Register PINB – Port ...
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PORTD – Port D Data Register DDRD – Port D Data Direction Register PIND – Port D Input Pins Address PORTE – Port E Data Register DDRE – Port E Data Direction Register PINE – Port E Input Pins Address ...
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PORTG – Port G Data Register DDRG – Port G Data Direction Register PING – Port G Input Pins Address PORTH – Port H Data (1) Register DDRH – Port H Data Direction (1) Register PINH – Port H Input ...
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Timer/Counter0 with PWM Overview Registers 2552H–AVR–11/06 Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse ...
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Definitions Timer/Counter Clock Sources Counter Unit ATmega329/3290/649/6490 90 event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. Many register and bit references in this section are written in general form. ...
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Output Compare Unit 2552H–AVR–11/06 Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk T0 clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected ...
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Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit ATmega329/3290/649/6490 92 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and ...
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Compare Output Mode and Waveform Generation 2552H–AVR–11/06 Figure 31. Compare Match Output Unit, Schematic COMnx1 Waveform COMnx0 Generator FOCn clk I/O The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of ...
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Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega329/3290/649/6490 94 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) ...
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Fast PWM Mode 2552H–AVR–11/06 to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before ...
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Phase Correct PWM Mode ATmega329/3290/649/6490 96 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM ...
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Figure 34. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 1 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each time ...
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Timer/Counter Timing Diagrams ATmega329/3290/649/6490 98 • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. ...
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Timer/Counter Register Description TCCR0A – Timer/Counter Control Register A 2552H–AVR–11/06 Figure 38 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 38. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f ...
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ATmega329/3290/649/6490 100 Table 55. Waveform Generation Mode Bit Description WGM01 WGM00 Timer/Counter Mode (CTC0) (PWM0) Mode of Operation Normal PWM, Phase Correct CTC Fast PWM Note: 1. The ...
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TCNT0 – Timer/Counter Register 2552H–AVR–11/06 Table 58. Compare Output Mode, Phase Correct PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected Reserved 1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare ...
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OCR0A – Output Compare Register A TIMSK0 – Timer/Counter 0 Interrupt Mask Register TIFR0 – Timer/Counter 0 Interrupt Flag Register ATmega329/3290/649/6490 102 Bit 0x27 (0x47) Read/Write R/W R/W R/W Initial Value The Output Compare ...
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Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source 2552H–AVR–11/06 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The Timer/Counter ...
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GTCCR – General Timer/Counter Control Register ATmega329/3290/649/6490 104 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock ...
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Timer/Counter1 Overview 2552H–AVR–11/06 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Registers ATmega329/3290/649/6490 106 Figure 41. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 29 on page 68, and Table 35 on page 72 ...
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Definitions Compatibility 2552H–AVR–11/06 also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the ...
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Accessing 16-bit Registers ATmega329/3290/649/6490 108 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; Save ...
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Reusing the Temporary High Byte Register ATmega329/3290/649/6490 110 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ...
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Timer/Counter Clock Sources Counter Unit 2552H–AVR–11/06 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in ...
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Input Capture Unit ATmega329/3290/649/6490 112 how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 117. The Timer/Counter Overflow Flag (TOV1) is set ...
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Input Capture Trigger Source Noise Canceler Using the Input Capture Unit 2552H–AVR–11/06 The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the ...
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Output Compare Units ATmega329/3290/649/6490 114 The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer ...
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Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit 2552H–AVR–11/06 (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). ...
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Compare Match Output Unit ATmega329/3290/649/6490 116 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control ...
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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2552H–AVR–11/06 The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = ...
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Fast PWM Mode ATmega329/3290/649/6490 118 Figure 46. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag ...
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit ...
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Phase Correct PWM Mode ATmega329/3290/649/6490 120 double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare ...
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OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: R PCPWM In phase correct PWM mode the counter is ...
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Phase and Frequency Correct PWM Mode ATmega329/3290/649/6490 122 ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of ...
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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP ...
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Timer/Counter Timing Diagrams ATmega329/3290/649/6490 124 non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 1 on page 127). The actual OC1x value will only be visi- ble on the port pin ...
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Figure 51. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 52 shows the count sequence close to TOP in various modes. When using phase ...
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Timer/Counter Register Description TCCR1A – Timer/Counter1 Control Register A ATmega329/3290/649/6490 126 Figure 53. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and ...
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Table 62 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 62. Compare Output Mode, Fast PWM COM1A1/COM1B1 COM1A0/COM1B0 Note special ...
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Table 64. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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TCCR1C – Timer/Counter1 Control Register C 2552H–AVR–11/06 (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in ...
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TCNT1H and TCNT1L – Timer/Counter1 OCR1AH and OCR1AL – Output Compare Register 1 A OCR1BH and OCR1BL – Output Compare Register 1 B ICR1H and ICR1L – Input Capture Register 1 ATmega329/3290/649/6490 130 Bit (0x85) (0x84) Read/Write ...
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TIMSK1 – Timer/Counter1 Interrupt Mask Register TIFR1 – Timer/Counter1 Interrupt Flag Register 2552H–AVR–11/06 Bit (0x6F) – – ICIE1 Read/Write R R R/W Initial Value • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable ...
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ATmega329/3290/649/6490 132 • Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out- put Compare Register A (OCR1A). Note that a Forced Output ...
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Timer/Counter2 with PWM and Asynchronous Operation Overview Registers 2552H–AVR–11/06 Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, ...
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Definitions Timer/Counter Clock Sources Counter Unit ATmega329/3290/649/6490 134 ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output ...
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Output Compare Unit 2552H–AVR–11/06 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock ...
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Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit ATmega329/3290/649/6490 136 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare ...
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Compare Match Output Unit Compare Output Mode and Waveform Generation 2552H–AVR–11/06 The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Gener- ator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare match. ...
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Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega329/3290/649/6490 138 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) ...
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Fast PWM Mode 2552H–AVR–11/06 compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A ...
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Phase Correct PWM Mode ATmega329/3290/649/6490 140 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM ...
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Figure 60. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each time ...
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Timer/Counter Timing Diagrams ATmega329/3290/649/6490 142 • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. ...
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Figure 63. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 64 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. ...
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Timer/Counter Register Description TCCR2A – Timer/Counter Control Register A ATmega329/3290/649/6490 144 Bit (0xB0) FOC2A WGM20 COM2A1 Read/Write W R/W R/W Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A ...
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Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the ...
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TCNT2 – Timer/Counter Register OCR2A – Output Compare Register A ATmega329/3290/649/6490 146 The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 71. Table 71. Clock Select Bit Description CS22 CS21 CS20 0 ...
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Asynchronous operation of the Timer/Counter ASSR – Asynchronous Status Register 2552H–AVR–11/06 Bit (0xB6) – – – Read/Write Initial Value • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is ...
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Asynchronous Operation of Timer/Counter2 ATmega329/3290/649/6490 148 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for ...
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TIMSK2 – Timer/Counter2 Interrupt Mask Register TIFR2 – Timer/Counter2 Interrupt Flag Register 2552H–AVR–11/06 • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up ...
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Timer/Counter Prescaler ATmega329/3290/649/6490 150 (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in ...
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GTCCR – General Timer/Counter Control Register 2552H–AVR–11/06 Bit TSM – – 0x23 (0x43) Read/Write R Initial Value • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 ...
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SPI – Serial Peripheral Interface Overview ATmega329/3290/649/6490 152 The ATmega329/3290/649/6490 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • ...
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Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master ...
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ATmega329/339/649/659 154 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 72. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 65. (1) ...
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SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait ...
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ATmega329/339/649/659 156 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; ...
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SS Pin Functionality Slave Mode Master Mode SPCR – SPI Control Register 2552H–AVR–11/06 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO ...
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ATmega329/339/649/659 158 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is ...
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SPSR – SPI Status Register SPDR – SPI Data Register 2552H–AVR–11/06 Bit 0x2D (0x4D) SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial ...
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Data Modes ATmega329/339/649/659 160 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 68 and Figure 69. ...
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USART0 Overview 2552H–AVR–11/06 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • ...
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AVR USART vs. AVR UART – Compatibility Clock Generation ATmega329/3290/649/6490 162 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by ...
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Internal Clock Generation – The Baud Rate Generator 2552H–AVR–11/06 Figure 71. Clock Generation Logic, Block Diagram UBRR fosc UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock ...
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Double Speed Operation (U2Xn) External Clock ATmega329/3290/649/6490 164 Table 77. Equations for Calculating Baud Rate Register Setting Equation for Calculating Operating Mode Asynchronous Normal BAUD mode (U2Xn = 0) Asynchronous Double Speed mode BAUD (U2Xn = 1) Synchronous Master BAUD ...
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Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either Frame Formats 2552H–AVR–11/06 clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data ...
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Parity Bit Calculation USART Initialization ATmega329/3290/649/6490 166 Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, ...
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Assembly Code Example USART_Init: ; Set baud rate out UBRR0H, r17 out UBRR0L, r16 ; Enable receiver and transmitter ldi r16, (1<<RXEN0)|(1<<TXEN0) out UCSR0B,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<USBS0)|(3<<UCSZ00) out UCSR0C,r16 ret (1) ...
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Data Transmission – The USART Transmitter Sending Frames with Data Bit ATmega329/3290/649/6490 168 The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port ...
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Sending Frames with 9 Data Bit 2552H–AVR–11/06 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following ...
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Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter ATmega329/3290/649/6490 170 The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data ...
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Data Reception – The USART Receiver Receiving Frames with Data Bits Receiving Frames with 9 Data Bits 2552H–AVR–11/06 The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCS- RnB Register to one. ...
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ATmega329/3290/649/6490 172 The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. (1) Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSR0A, RXC0 rjmp USART_Receive ; ...
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Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker 2552H–AVR–11/06 The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag ...
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Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery ATmega329/3290/649/6490 174 In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn ...
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Asynchronous Data Recovery 2552H–AVR–11/06 Figure 74. Start Bit Sampling RxD IDLE Sample (U2X = Sample (U2X = When the clock recovery logic detects a high (idle) to low (start) ...
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Asynchronous Operational Range ATmega329/3290/649/6490 176 Figure 76. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = Sample (U2X = The same majority voting is done to the ...
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Table 78. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = (Data+Parity Bit) R (%) R slow 5 93.20 6 94.12 7 94.81 8 95.36 9 95.81 10 96.17 Table 79. Recommended Maximum ...
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Multi-processor Communication Mode Using MPCM ATmega329/3290/649/6490 178 Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not ...
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USART Register Description UDRn – USART I/O Data Register n UCSRnA – USART Control and Status Register n A 2552H–AVR–11/06 Bit Read/Write R/W R/W R/W Initial Value The USART Transmit Data Buffer Register and ...
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UCSRnB – USART Control and Status Register n B ATmega329/3290/649/6490 180 • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first ...
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UCSRnC – USART Control and Status Register n C 2552H–AVR–11/06 • Bit 3 – TXENn: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override nor- mal port operation for the TxD pin when enabled. ...
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UBRRnL and UBRRnH – USART Baud Rate Registers n ATmega329/3290/649/6490 182 • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 82. ...
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Examples of Baud Rate Setting Table 85. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2Xn = 0 Rate (bps) UBRRn Error UBRRn 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 ...
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Table 86. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 87. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 88. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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USI – Universal Serial Interface Overview 2552H–AVR–11/06 The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code ...
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Functional Descriptions Three-wire Mode ATmega329/3290/649/6490 188 selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It ...
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Figure 79. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 USCK USCK DO MSB 6 DI MSB The Three-wire mode timing is shown in Figure 79. At the top of the figure ...
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SPI Master Operation Example ATmega329/3290/649/6490 190 The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: sts USIDR,r16 ldi r16,(1<<USIOIF) sts USISR,r16 ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) SPITransfer_loop: sts USICR,r16 lds r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop ...
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SPI Slave Operation Example 2552H–AVR–11/06 The following code demonstrates how to use the USI module as a SPI Master with max- imum speed (fsck = fck/4): SPITransfer_Fast: sts USIDR,r16 ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC) ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK) sts USICR,r16 ; MSB sts USICR,r17 sts ...
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Two-wire Mode ATmega329/3290/649/6490 192 ferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs ...
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Figure 81. Two-wire Mode, Typical Timing Diagram SDA SCL ADDRESS R Referring to the timing diagram (Figure 81.), a bus transfer involves the following steps: 1. The a start condition ...
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Start Condition Detector Clock speed considerations. Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt ATmega329/3290/649/6490 194 The start condition detector is shown in Figure 82. The SDA line is delayed (in ...
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USI Register Descriptions USIDR – USI Data Register USISR – USI Status Register 2552H–AVR–11/06 Bit (0xBA) MSB Read/Write R/W R/W R/W Initial Value The USI uses no buffering of the Serial Register, i.e., when ...
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ATmega329/3290/649/6490 196 When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal ...
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USICR – USI Control Register 2552H–AVR–11/06 Bit (0xB8) USISIE USIOIE USIWM1 Read/Write R/W R/W R/W Initial Value The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. • ...
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ATmega329/3290/649/6490 198 Table 89. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 Description 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal Three-wire mode. Uses DO, DI, and USCK pins. The Data ...
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Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the ...
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Analog Comparator Overview ADCSRB – ADC Control and Status Register B ACSR – Analog Comparator Control and Status Register ATmega329/3290/649/6490 200 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the ...