ATMEGA329V-8AU Atmel, ATMEGA329V-8AU Datasheet - Page 199

• Manufacturer Part Number: ATMEGA329V-8AU
• Description: IC AVR MCU 32K 8MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• A/d Inputs: 8-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 54
• Interface: SPI/UART/USART/USI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 32K Bytes
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.7-5.5 V
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2552H–AVR–11/06
• Bit 3..2 – USICS1..0: Clock Source Select
These bits set the clock source for the Shift Register and counter. The data output latch
ensures that the output is changed at the opposite edge of the sampling of the data
input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or
Timer/Counter0 Compare Match clock option is selected, the output latch is transparent
and therefore the output is changed immediately. Clearing the USICS1..0 bits enables
software strobe option. When using this option, writing a one to the USICLK bit clocks
both the Shift Register and the counter. For external clock source (USICS1 = 1), the
USICLK bit is no longer used as a strobe, but selects between external clocking and
software clocking by the USITC strobe bit.
Table 90 shows the relationship between the USICS1..0 and USICLK setting and clock
source used for the Shift Register and the 4-bit counter.
Table 90. Relations between the USICS1..0 and USICLK Setting
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the
counter to increment by one, provided that the USICS1..0 bits are set to zero and by
doing so the software clock strobe option is selected. The output will change immedi-
ately when the clock strobe is executed, i.e., in the same instruction cycle. The value
shifted into the Shift Register is sampled the previous instruction cycle. The bit will be
read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is
changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this
case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 90).
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from
1 to 0. The toggling is independent of the setting in the Data Direction Register, but if the
PORT value is to be shown on the pin the DDRE4 must be set as output (to one). This
feature allows easy clock generation when implementing master devices. The bit will be
read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to
one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an
early detection of when the transfer is done when operating as a master device.
USICS1
0
0
0
1
1
1
1
USICS0
0
0
1
0
1
0
1
USICLK
X
0
1
0
0
1
1
Shift Register Clock
Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, positive edge
External, negative edge
External, positive edge
External, negative edge
ATmega329/3290/649/6490
4-bit Counter Clock
Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 Compare
Match
External, both edges
External, both edges
Software clock strobe
(USITC)
Software clock strobe
(USITC)
199