ATMEGA3250P-20AU Atmel, ATMEGA3250P-20AU Datasheet - Page 310

• Manufacturer Part Number: ATMEGA3250P-20AU
• Description: IC MCU AVR 32K FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250P-20AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA3250P-16AU; ATMEGA3250P-16AU

26.9
Table 26-7.
Notes:
8023F–AVR–07/09
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
SPI Timing Characteristics
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
SPI Timing Parameters
CLCL
CLCL
SS high to tri-state
SCK to out high
SCK to SS high
SCK high/low
for f
for f
SS low to SCK
SCK high/low
Rise/Fall time
Rise/Fall time
SS low to out
Description
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
CK
CK
Setup
Setup
Hold
Hold
< 12 MHz
> 12 MHz
See
Figure 26-4. SPI Interface Timing Requirements (Master Mode)
Figure 26-4
(1)
(Data Output)
(Data Input)
(CPOL = 0)
(CPOL = 1)
MISO
MOSI
SCK
SCK
SS
and
Figure 26-5
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
6
4
MSB
5
MSB
for details.
20 • t
4 • t
2 • t
Min
10
20
t
7
ck
ck
ck
ck
...
See
...
Table 17-4 on page 161
50% duty cycle
0.5 • t
ATmega325P/3250P
Typ
3.6
1.6
10
10
10
10
15
15
10
sck
2
LSB
1
LSB
2
Max
3
8
ns
µs
ns
310